Field-Programmable Gate Arrays

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DVI - LVDS controller

Hello all, I am thinking of building a device which will convert DVI output from my graphics card to LVDS to drive my L...
3 comments posted 20yrs
posted by mynameiskev
3 comments posted 20yrs posted by mynameiskev

multiphase data extraction question

Hi, Reading the http://www.xilinx.com/publications/books/serialio/serialio-ch3.pdf you can see in fig 3-5 pg .24 and in...
6 comments posted 20yrs
posted by sdroamt
6 comments posted 20yrs posted by sdroamt

Problem with multple clcok domains

Hi I am writing synthesizable Verilog code for a DPRAM. It has two ports, Port A and Port B. For each port theres is a...
3 comments posted 20yrs
posted by shiladitya.biswas
3 comments posted 20yrs posted by shiladitya.biswas

Parameterized Comparator Verilog Code

Hello: I am trying to write some code for a comparator. Is it possible to write the code as so module comparator(A_lt_B...
1 comments posted 20yrs
posted by prasunp
1 comments posted 20yrs posted by prasunp

Inferring Adder with Carry In and Cary out

Hi All, I am trying to infer a adder with a carry in and carry out in Xilinx ISE 7.1. For the unsigned adder case it is...
0 comments posted 20yrs
posted by Sudhir.Singh
0 comments posted 20yrs posted by Sudhir.Singh

FPGA - software or hardware?

Does a VHDL programmed FPGA concern software or hardware? As usual also this issue can be approached from different vie...
41 comments posted 20yrs
posted by hub_antispam
41 comments posted 20yrs posted by hub_antispam

FPGA Board Competition

In addition to the competition we are running currently running we are also running one in conjuction with Components I...
0 comments posted 20yrs
posted by removethisthenleavejea
0 comments posted 20yrs posted by removethisthenleavejea

help with VGA timings

Hi, I'm new in fpgas.I've been researching about vga timings for a few days, but all information I've found it's confus...
10 comments posted 20yrs
posted by a80x86
10 comments posted 20yrs posted by a80x86

Addressing BRAM in a V2 pro

Hi all, I'm designing a IP core for a Virtex 2 pro board. This IP need to store data in BRAM. I have been searching how...
6 comments posted 20yrs
posted by michiel.vanderlinden
6 comments posted 20yrs posted by michiel.vanderlinden

FPT'06: First Call-for-paper

Please see the following details. Warm regards, Theerayod Wiangong Mahanakorn University, Bangkok, Thailand =3D=3D=3D=3...
0 comments posted 20yrs
posted by wiangtong
0 comments posted 20yrs posted by wiangtong

MontaVista Linux and Virtex-II & 4

Does anyone know if MontaVista Linux or other distributions support SMP in Virtex-II Pro and Virtex-4? Thanks.
6 comments posted 20yrs
posted by orange_tabby_go
6 comments posted 20yrs posted by orange_tabby_go

Xilinx ISE Simulator Arrays

The ISE 7.1i Simulator has trouble displaying the array in the code below. Specifically when the mem array is added to...
1 comments posted 20yrs
posted by bradsmallridge
1 comments posted 20yrs posted by bradsmallridge