Dear Sir, We want to use JHDL for our Firewall development. Can tell us please, in which format the JHDL generates output & if thi generated output format can be programmed in a Xilinx FPGA and Alter FPGA. My second query is, whether this generated output format from JHD can be combined with other VHDL generated output format (let's say ".mcs or ".bit" file of Xilinx) & then overall program can be fused to particular FPGA. Like, we want to develop our Firewall application usin JHDL & PCI interface application using Xilinx VHDL. These two application has to be combined & then programmed into Xilinx FPGA.
Thanks & regards, varindra