Hi all, I am new to this group and i am facing one problem regardin reading from the sdram. Actually I am accessing sdram indirectly through CPU. So I am writin write data into the fpga registers and set the wr_start bit, afte completing the write operation wr_start bit will be cleared indicatin write has completed. To verify the data written to sdram i am setting th read_start and reading immediately and the data is correct. But if i rea after sometime the data i am getting is FFFF FFFF (two 16 bit sdrams). am operating sdram (SDR sdram) at 125 Mhz. Is this because of auto refresh is not done properly? But i am accessing sdrams on the board. Sometime one the sdram works and remaining fails. Can anyone has idea? or require more info to answer. Thanks in advance.