Latest threads in Field-Programmable Gate Arrays

PowerPC based SoC design, getting it working from first attempt

The speaker at Xilinx presentation at Embedded World asked the crowd: "Has anyone managed to create an FPGA System On C...

3 20yrs

Antti.Lukats

3 20yrs Antti.Lukats

configuring stratix GX Fpga

Hello, I am using stratix fpga for a design of mine and i am using Bank 4 for GTL interface and so that IO bank is supp...

1 20yrs

praveenkumar.bm

1 20yrs praveenkumar.bm

doubt

Hi can any body explain i am working on ddrsdram controller .in sample synthesis script i got like this while giving ti...

1 20yrs

venkatec

1 20yrs venkatec

RC1000pp with XCV400

Hi, I am working with JBits 2.8 & the RC1000pp board. I have a system up & running where i can configure the RC1000pp b...

0 20yrs

colin.mullaney

0 20yrs colin.mullaney

Virtex-4 Output Primitive

Hello group, I wish to replaced the inferred tri-state pins shown in the code below with primitives. How do I do that?...

0 20yrs

bradsmallridge

0 20yrs bradsmallridge

Cannot use ML310 DDR

hi, i'm trying to work with the ddr sdram on the ml310 development board. i tried creating a simple base system with th...

3 20yrs

king.azman

3 20yrs king.azman

Layer 2 (MAC) Research Project to Eliminate Routers

We are a startup company of 6 employees (2 full time) which is the exclusive licensee of the patented ideal optimum MAC...

1 20yrs

jonathangael

1 20yrs jonathangael

Xilinx ISE 6.3 confusion with CPLD logic results

My VHDL project has out grown a XC95108 CPLD, so I'll be using a XC95144 instead. After running the ISE synthesizer and...

2 20yrs

vze24h5m

2 20yrs vze24h5m

How to make Customized IP which connected with Microblaze through FSL access the OPB bus?

I build a system which has a MicroBlaze, a LMB connect BRAM for local instruction/data memory (8KB) and an OPB connecte...

11 20yrs

hy34

11 20yrs hy34

bypass between ilogic and ologic

I'm using ISE 8.1.02. I seem to be having trouble making the BYPASS attribute work on nets. As I understand it, it is s...

1 20yrs

brannonking

1 20yrs brannonking

Relative placement constraints in Xilinx ISE w/ Verilog

I am building a design which consists of a two-dimensional array of smalll processing elements, each of which contains...

1 20yrs

nestorj

1 20yrs nestorj

Virtex2: can I really just leave M1,M2,M3 pins floating?

Hi all, for a Virtex II part, for slave serial mode, can I REALLY leave M1, M2, M3 pins floating or is it safer to tie t...

1 20yrs

geewhiz1

1 20yrs geewhiz1

fix: Xilinx USB Platform Cable on linux 2.6

Hi! A while back sombody posted about problems with his Xilinx USB cable It took some time to get it working, there are...

2 20yrs

google.com

2 20yrs google.com

How to use Gigabit transciever

Hello Groups, I am planning to use gigabit transceiver (Stratix GX), so wanted to know what additional glue logic i hav...

1 20yrs

praveenkumar.bm

1 20yrs praveenkumar.bm

EDK 8.1 SP1 released, DDR2 support is now included !!

Hi EDK 8.1 SP1 was made available already on 17 Feb so a few days earlier then expected, and PLB DDR2 memory IP core is...

0 20yrs

Antti.Lukats

0 20yrs Antti.Lukats

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