Field-Programmable Gate Arrays

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configuring stratix GX Fpga

Hello, I am using stratix fpga for a design of mine and i am using Bank 4 for GTL interface and so that IO bank is supp...
1 comments posted 20yrs
posted by praveenkumar.bm
1 comments posted 20yrs posted by praveenkumar.bm

doubt

Hi can any body explain i am working on ddrsdram controller .in sample synthesis script i got like this while giving ti...
1 comments posted 20yrs
posted by venkatec
1 comments posted 20yrs posted by venkatec

RC1000pp with XCV400

Hi, I am working with JBits 2.8 & the RC1000pp board. I have a system up & running where i can configure the RC1000pp b...
0 comments posted 20yrs
posted by colin.mullaney
0 comments posted 20yrs posted by colin.mullaney

Virtex-4 Output Primitive

Hello group, I wish to replaced the inferred tri-state pins shown in the code below with primitives. How do I do that?...
0 comments posted 20yrs
posted by bradsmallridge
0 comments posted 20yrs posted by bradsmallridge

Cannot use ML310 DDR

hi, i'm trying to work with the ddr sdram on the ml310 development board. i tried creating a simple base system with th...
3 comments posted 20yrs
posted by king.azman
3 comments posted 20yrs posted by king.azman

Layer 2 (MAC) Research Project to Eliminate Routers

We are a startup company of 6 employees (2 full time) which is the exclusive licensee of the patented ideal optimum MAC...
1 comments posted 20yrs
posted by jonathangael
1 comments posted 20yrs posted by jonathangael

Xilinx ISE 6.3 confusion with CPLD logic results

My VHDL project has out grown a XC95108 CPLD, so I'll be using a XC95144 instead. After running the ISE synthesizer and...
2 comments posted 20yrs
posted by vze24h5m
2 comments posted 20yrs posted by vze24h5m

bypass between ilogic and ologic

I'm using ISE 8.1.02. I seem to be having trouble making the BYPASS attribute work on nets. As I understand it, it is s...
1 comments posted 20yrs
posted by brannonking
1 comments posted 20yrs posted by brannonking

fix: Xilinx USB Platform Cable on linux 2.6

Hi! A while back sombody posted about problems with his Xilinx USB cable It took some time to get it working, there are...
2 comments posted 20yrs
posted by google.com
2 comments posted 20yrs posted by google.com

How to use Gigabit transciever

Hello Groups, I am planning to use gigabit transceiver (Stratix GX), so wanted to know what additional glue logic i hav...
1 comments posted 20yrs
posted by praveenkumar.bm
1 comments posted 20yrs posted by praveenkumar.bm

DSP

Please Give me outline of doing a project of dsp processor design.
1 comments posted 20yrs
posted by sahi.cse
1 comments posted 20yrs posted by sahi.cse