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configuring stratix GX Fpga

Hello, I am using stratix fpga for a design of mine and i am using Bank 4 for GTL interface and so that IO bank is supplied with 1.5 V and Vref is

1v. But this bank has some of the configuration pins and TDO is one of them. It is said that TDO reqiures 3.3 V in the configuration datasheet. But since this IO bank is given 1.5 V. So this may create problem in configuration. Can you please suggest a solution for this?

Thanks and regards Praveen

Reply to
pinku
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HI praveen TDO JTAG interfce pin u can give bank voltage it will not create any problem go ahead venkat

Reply to
venkatec

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