Hello, I am using stratix fpga for a design of mine and i am using Bank 4 for GTL interface and so that IO bank is supplied with 1.5 V and Vref is
1v. But this bank has some of the configuration pins and TDO is one of them. It is said that TDO reqiures 3.3 V in the configuration datasheet. But since this IO bank is given 1.5 V. So this may create problem in configuration. Can you please suggest a solution for this?
Thanks and regards Praveen