doubt

Hi

can any body explain i am working on ddrsdram controller .in sample synthesis script i got like this while giving timing setings in assinment editor (quartusII software)

pls explain what is the meaning of under lines i.e

create clk period10_waveform{0,5} find (port,"clk")

setclock_skewclk-minus uncertinty0.25-plus uncertinty0.25

dclk_arrival is the arrival time of dclk relative to clk input

and include tck_dealy cell

create_clock-period10_waveform{0,5}find(port,"dclk")

set_clock_skew dclk_dealy DCLK_ARRIVAL-minus_uncertainty0.25,

plus_uncertainty

pls anybody tel what is that how to give ?explain all the things?

advanced thanks venki