can any body explain i am working on ddrsdram controller .in sample synthesis script i got like this while giving timing setings in assinment editor (quartusII software)

pls explain what is the meaning of under lines i.e

create clk period10_waveform{0,5} find (port,"clk")

setclock_skewclk-minus uncertinty0.25-plus uncertinty0.25

dclk_arrival is the arrival time of dclk relative to clk input

and include tck_dealy cell


set_clock_skew dclk_dealy DCLK_ARRIVAL-minus_uncertainty0.25,


pls anybody tel what is that how to give ?explain all the things?

advanced thanks venki

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Hi Venki,

If you open the assignent editor (Ctrl-Shift-A) after running the script, you should see the equivalent assignments in a more readable format.

To see the relationship between the clock domains clk and dclk, go to Assignments->Settings->Timing Settings.

Best regards,


Reply to
Ben Twijnstra

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