Field-Programmable Gate Arrays

speed control ac motor in FPGA

I need help about controlling the speed of an ac trifasic motor, thanks

5 comments posted 20yrs

posted by feedcaseg

5 comments posted 20yrs posted by feedcaseg

Digilent Spartan-3 Starter Kit w/ JTAG-USB Problem/Solution

Well, I'm not sure if anyone here has had the same problem, but I have, and it has been driving me nuts. My primary mac...

14 comments posted 20yrs

posted by none

14 comments posted 20yrs posted by none

for all those who believe in ASICs....

http://www.eetimes.com/news/semi/showArticle.jhtml;jsessionid=2VY5CYWYDOXWUQSNDBCSKH0CJUMEKJVN?articleID=181501385 Well...

175 comments posted 20yrs

posted by austin

175 comments posted 20yrs posted by austin

Questions about counter in VHDL

I have implemented a 8-bit synchronous counter by VHDL. The result is that the LED display show continuously running th...

13 comments posted 20yrs

posted by sandypure

13 comments posted 20yrs posted by sandypure

recommendation for JTAG Boundary Scan software??

Can anyone recommend some rea$onable software for doing JTAG boundary scan? I have a design with some CPLD's that are B...

5 comments posted 20yrs

posted by clement

5 comments posted 20yrs posted by clement

Call for Papers: IMECS 2006 (the multiconference of 14 engineering & computer science conferences)

CFP From: International Association of Engineers (http://www.iaeng.org) Engineering Letters (http://www.engineeringlett...

0 comments posted 20yrs

posted by imecs_2006

0 comments posted 20yrs posted by imecs_2006

Xilinx ISE8.1 & MIG1.5 crash

hello all, I just downloaded Xilinx ISE8.1 and Memory Interface Generator MIG1.5. I selected a DDR2-Sodimm to implement...

1 comments posted 20yrs

posted by ask

1 comments posted 20yrs posted by ask

Xilinx LVDS

Hi, I want to findout the minimum accepted voltage difference for LVDS in Xilinx Spartan3 FPGAs. For example is 40mV acc...

6 comments posted 20yrs

posted by hakan.sakman

6 comments posted 20yrs posted by hakan.sakman

Atmel using Xilinx FPGAs

Whilst reading the current issue of Atmel's Applications Journal I was intrigued to see that they are using Xilinx FPGAs...

1 comments posted 20yrs

posted by leon_heller

1 comments posted 20yrs posted by leon_heller

Internal pull down on the FPGA.....

Hi all, I am facing a problem with my design. In which i assigned tri state buffers to drive a bus which is connected t...

2 comments posted 20yrs

posted by vssumesh_asic

2 comments posted 20yrs posted by vssumesh_asic

Internal Signals in OPB EMC In XIlinx PLatform studio

HI how would i use internal signals in XPS for microblaze on spartan 3 fpga board. let me explain my project in opb_emc...

4 comments posted 20yrs

posted by sachink321

4 comments posted 20yrs posted by sachink321

Microblaze multiplier Virtex2pro vs. Spartan3e

If I compile my Microblaze project for Virtex2pro, the compiler uses the mul instruction (hw multiplier) as expected. I...

1 comments posted 20yrs

posted by alan

1 comments posted 20yrs posted by alan

A few questions about FPGAs

I had two basic questions about FPGAs and I wanted to know what you guys thought about those: 1. Are FPGAs mostly PALs...

2 comments posted 20yrs

posted by mahurshi

2 comments posted 20yrs posted by mahurshi

Terminologie/knowledge issu

Hi all, What's that mean : "Low Level Verification of ASIC Soc"?. The SoC should be tested on development board contain...

3 comments posted 20yrs

posted by thomas.b36

3 comments posted 20yrs posted by thomas.b36

Retiming a datapath

Hi, i've a problem using xilinx xst synthesis tool. I need to do the retiming of a combinatorial datapath. I followed t...

0 comments posted 20yrs

posted by giovannibusonera

0 comments posted 20yrs posted by giovannibusonera