Hi all, I am facing a problem with my design. In which i assigned tri state buffers to drive a bus which is connected to sixteen identical blocks. This bus is controlling the register updation. But in the default configuration when all blocks are driving high impedance to the bus the bus is going to '1' state by internal pull up. I want to know is there any way to pull down the internal signals in the Xilinx FPGA (specifically Virtex 4 or Virtex E). regards Sumesh V S
- posted
18 years ago