hello all, I just downloaded Xilinx ISE8.1 and Memory Interface Generator MIG1.5. I selected a DDR2-Sodimm to implement in a Virtex4. MIG1.5 generates a complete synthesizable testbench and the batch file "ise_flow.bat" When I start the batch file all works fine till xilinx map tool stops with an internal error: FATAL_ERROR:Map:Portability/export/Port_Main.h:127:1.24. Is there anybody with same problem on MIG1.5 thanks for help peter
- posted
18 years ago