Field-Programmable Gate Arrays

Hitech Global

Someone posted here about a year ago asking if anyone had experience with Xilinx development boards from Hitech Global...

0 comments posted 20yrs

posted by rsefton

0 comments posted 20yrs posted by rsefton

Asynchronous FIFO design question

Hi, I have some problem detecting the full and empty conditions in an asynchronous FIFO design. Hope any of you can hel...

12 comments posted 20yrs

posted by m.adithya

12 comments posted 20yrs posted by m.adithya

ac97 codec on xupv2p

Hi all, I'm trying to use the ac97 codec on the virtex-ii pro development system for a project. The ac97 codec is attac...

0 comments posted 20yrs

posted by dasani8888

0 comments posted 20yrs posted by dasani8888

Power estimates in XC3S1500

Dear Abby, I have a coworker who is calculating the FPGA power required for a rather low speed design we are doing. The...

4 comments posted 20yrs

posted by spamgoeshere4

4 comments posted 20yrs posted by spamgoeshere4

what do the following constraints mean?

Hi all, I am trying to modify some code and I came across these constraints. 'clk_in' is the input clock and 'clk' is g...

6 comments posted 20yrs

posted by subhasri.krishnan

6 comments posted 20yrs posted by subhasri.krishnan

Simulating a ppc working with external memory

Hi all, I would like to create a simulation for a v4fx design containing a ppc. My instrutions memory is located on ext...

1 comments posted 20yrs

posted by me_2003

1 comments posted 20yrs posted by me_2003

Vccaux regulator

Hi, I need someone more experinced to confirm me if the TPS54610 I have choosen for the 2.5V voltage supply of my Spart...

3 comments posted 20yrs

posted by marco

3 comments posted 20yrs posted by marco

latticexp

I see something but I am not sure.. am i dreaming? Can LatticeXP be supplied with only 3.3V linear voltage regulator? yu...

1 comments posted 20yrs

posted by yusufilker

1 comments posted 20yrs posted by yusufilker

Pullup questions on Spartan3

Hi, Spartan3 does have internal pullup and pulldown resistors on all its I/O. I'll work with LVCMOS33. I have to commun...

7 comments posted 20yrs

posted by marco

7 comments posted 20yrs posted by marco

processor bus tristate at two places

Hi, I have my VHDL modules which access the processor bus. I have one more third party core wher in at also uses the pr...

2 comments posted 20yrs

posted by praveen.kantharajapura

2 comments posted 20yrs posted by praveen.kantharajapura

Simulation of Xilinx Rocket IO

Hello All, I want to use Xilinx v2p or v4 rocket IOs in one of my designs. right now I am using Xilinx webpack 8.1 and...

5 comments posted 20yrs

posted by kedarpapte

5 comments posted 20yrs posted by kedarpapte

How to interface ASIC on a PCB and and an FPGA

Hi, I have a custom ASIC and I would like to interface this with my XUP V2P (Xilinx VII Pro) board. I am new to using t...

2 comments posted 20yrs

posted by bis

2 comments posted 20yrs posted by bis

ISE freezing up with picoblaze code.

I'm trying to create a project in ISE webpack 8.1i. Whenever I try and add Picoblaze vhdl into the project it freezes n...

0 comments posted 20yrs

posted by zhangweidai

0 comments posted 20yrs posted by zhangweidai

How to choose FPGA/CPLD ?

Hi, I am a beginner in the vlsi industry.I am having a doubt.Whenever we are starting soem project work,how can we deci...

4 comments posted 20yrs

posted by kulkarku

4 comments posted 20yrs posted by kulkarku

Par error in Spartan-3

I met problem while doing place for Spartan-3 in ISE 7.1 .They said. Number of BUFGMUXs 2 out of 8 25% Number of Extern...

6 comments posted 20yrs

posted by kent.mou

6 comments posted 20yrs posted by kent.mou