A few questions about FPGAs

I had two basic questions about FPGAs and I wanted to know what you guys thought about those:

  1. Are FPGAs mostly PALs and PLAs ?

  1. For large designs, how is the timing analysis done on FPGAs? Is it done using the libraries for the standard cells used or is it done only after the code is synthesized "for" the FPGA (which makes more sense)

Mahurshi Akilla

Reply to
Loading thread data ...

Very different technology difference. PAL/PLA designs are normally based on a fixed array of wire AND/OR functions. FPGA's are normally designed using lookup tables. See the data sheets for the devices.

It's normally done at several levels ... estimates of typical device and routing delays early in the project, and using better detailed numbers post place and route based on the actual finished design resources used.

Reply to


FPGAs are mostly made of both PLAs and PALs . FPGAs timing analysis is done after the code is synthesized. we dont do timing analysis using standard cells for FPGAs.we do timing alalysis in fpga only for the code. in fpga the design is already freezed,so we cannot do timing alalysis using standard cells.

regards selva bangalore

snipped-for-privacy@gmail.com wrote:

Reply to
selva kumar

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.