Field-Programmable Gate Arrays

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hwicap can be used in the virtex4

hi everyone! hwicap can be used in the virtex4 ? I try to use it but the EDK 7.1 tell me : error: MDT - opb_hwicap (opb...
12 comments posted 20yrs
posted by zhangxun0501
12 comments posted 20yrs posted by zhangxun0501

JTAG program failed

I have problems programming my EEPROM through JTAG. Most of the times it fails but I have succeeded once. When programm...
1 comments posted 20yrs
posted by mughat
1 comments posted 20yrs posted by mughat

test(null)

just a test
0 comments posted 20yrs
posted by pc_dragon
0 comments posted 20yrs posted by pc_dragon

Picoblaze, UART: need help!!

Thanks so much to all who replied to my previous messages I appreciate your concern. Please help me on this. I have wri...
1 comments posted 20yrs
posted by preet723
1 comments posted 20yrs posted by preet723

design compiler optimization

Hi, Does synopsys design compiler perform a TILOS based circuit optimization. TILOS is a iterative circuit sizing tool,...
1 comments posted 20yrs
posted by mahalingamv
1 comments posted 20yrs posted by mahalingamv

ISE 8.1, EDK 8.1 installation

I want to upgrade my EDK and ISE to 8.1 version from 7.1 versions.I am using linux OS. I want to ask those who have alr...
1 comments posted 20yrs
posted by nitesh.guinde
1 comments posted 20yrs posted by nitesh.guinde

no output from BUFGMUX

All- I'm using a BUFGMUX but consistently get no output, even though one clock is always active. I was hoping that if:...
1 comments posted 20yrs
posted by jbrower
1 comments posted 20yrs posted by jbrower

question about Virtex-II Pro program execution time

Hi, I'm working with a virtex-ii pro board. I don't have previous embedded system experience, so I have some wonders ab...
2 comments posted 20yrs
posted by dasani8888
2 comments posted 20yrs posted by dasani8888

BlockRAM

Hi, I want to share the BlockRAM between the PowerPC and user logic. I have 4 user logic blocks which would be connecte...
0 comments posted 20yrs
posted by faraz.khan
0 comments posted 20yrs posted by faraz.khan

Interface Problem

I am working on Xilinx Virtex4 FPGA and need to design a user IP which will interface to all the external sources like...
4 comments posted 20yrs
posted by faraz.khan
4 comments posted 20yrs posted by faraz.khan

Xilinx Schematic Entry

I am having an argument with another guy I work with about the Xilinx tools. He only draws his logic with the schematic...
19 comments posted 20yrs
posted by emh203
19 comments posted 20yrs posted by emh203

GTKWave 1.3.86 for Windows is available

Hi, I compiled the GTKWave 1.3.86 for Windows (win32 with Gtk 2.0) and put the files and instructions at http:www.dspia...
0 comments posted 20yrs
posted by kal*
0 comments posted 20yrs posted by kal*

Help needed

Hi considering me a novice. I have a very basic question. How can i connect multiple user IPs to a shared memory on FPG...
3 comments posted 20yrs
posted by faraz.khan
3 comments posted 20yrs posted by faraz.khan