Hi considering me a novice. I have a very basic question. How can i connect multiple user IPs to a shared memory on FPGA. I am using Xilinx Virtex 4 FX FPGA and want to have a common memory place on chip where i can save all the signal comming from out side. This common place will also be used to share the output signal between the custom IP. I am planning to use BRAM for this purpose but since BRAM is dual port so i can have only two of the IP attached to it at any time. Please advice me since this issue is halting my design process. I also want to attach the processor to that shared memory so it can also share the signals with rest of user logic residing on FPGA. I am using on chip processor PowerPC405.
Thanks
Faraz