Interface Problem

snipped-for-privacy@nssi.us schrieb:

That always a miracle. ;-) Serious, first you should think about the general concept of your design and not so much about the details.

Whats the purpose of this board? (Data aquisition? Digital filter? DSP ?) Whats the main data flow? Whats the main data processing? How should the data processing take place (State machine, embedded procssor, just buffering and processing using external processor/DSP?)

And some more. Then you can think about details. You can is microblaze as an embedded processor. This way you need IPs with a bus interface for microblaze. You might want to use on some more or less complex state machines. This way you are free to design you own internal interface.

Hope this helps.

Regards Falk

Hi Falk thanks for replying. I am using Virtex4FX and primarly my design will have some user logic embedded on the FPGA and PowerPC 405 Core. I am batteling on two fronts...

One to make a user logic on FPGA which will deal with all the I/O and process the data.

Second to connect this user logic to BRAM for storage so PowerPC can use the data. Things are not so simple as i will also have other user logic also along with this I/O logic which need to be connected to BRAM so they can access the data. I know that BRAM is dual port RAM so only two IPs can be attached. I have to use mux for data and address to make all the IPs access the BRAM as the other port of BRAM will be used by the processor. So leaving this problem aside. I am trying to UNDERSTAND how that I/O logic should be designed to grab all the data comming from outside FPGA. I/O logic will have some registers obviously how can i use these registers and how can i assign address to these.

Thanks

Faraz

snipped-for-privacy@nssi.us schrieb:

Hmmm, your not the first emperor, aeeehhm engineer, who tried this . . . And if history books are correct . . .

SCNR ;-)

Again, your talking is still confusing, and Iam afraid your thinking is similar. Sorry, no offence intented. Take a deep breath, relax, and start to draw a very basic diagramm of all major components. Draw arrows to indicated data and control flow. Look at your diagram. Think about it. Then, increase the details in the major components blocks.

Regards Falk

P.S. Iam afraid you are lacking some basic skills in FPGA design anyway, so maybe you should try to appoach this problem first.

You are right i am very new to FPGA and trying to get a basic idea of how the things work arround. You are also right that i should start from top level down. But i guess i am trying to do so. That's why i asked you how can i grab the data comming out of the FPGA into FPGA.

Thanks again

Faraz