design compiler optimization


Does synopsys design compiler perform a TILOS based circuit optimization.

TILOS is a iterative circuit sizing tool, published in 1985 by fishburn and dunlop.

any information and details about this is requested.



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Hi Mahalingam, your question is a little off topic for this newsgroup. But anyway...

have a look at this page:

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It's a short example of what TILOS does compared to dc. If you want to find out wether an actual version of dc can do the trick or not, give it a try (or ask the synopsys guys ;-) )

Enter the design and set a constraint on the power consumption of the circuit. See if the optimization results change with lower vaues for the power constraint. Don't forget to check your technical libraries wether they support cells with different drive strenght or not.

have a nice synthesis Eilert

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