Field-Programmable Gate Arrays

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USB Interface to Virtex-4

Hello All, I am looking for a time efficient means to add USB capability to a Virtex-4 LX80. After looking around it se...
23 comments posted 20yrs
posted by billingworth
23 comments posted 20yrs posted by billingworth

need your comments

Hi all, I need to get a feedback from you experts on some of the guidelines I adopted within my project with a Spartan3...
5 comments posted 20yrs
posted by marco
5 comments posted 20yrs posted by marco

USB phy in dev board

Hi all, I would like to ask if anyone has implemented a physical usb interface in a development board of altera that ha...
2 comments posted 20yrs
posted by aamanat
2 comments posted 20yrs posted by aamanat

problem block ram modelsim

Dear, I have a problem with my block-ram, namely I have made new perheperal (opb-ipif) and I by means of coregen dpram...
0 comments posted 20yrs
posted by bmwcabrio76
0 comments posted 20yrs posted by bmwcabrio76

PCB Bypass Caps

Hi I need to layout a Virtex 2 Pro board using a 672 BGA package. Does anyon have any tips for the placement of the byp...
22 comments posted 20yrs
posted by maxascent
22 comments posted 20yrs posted by maxascent

how can one get a netlist consisting of SLICEs?

How can one synthesize their Verilog code into FPGA SLICEs without doing PAR? I want the code to synthesize into SLICEs...
3 comments posted 20yrs
posted by imavroid
3 comments posted 20yrs posted by imavroid

FpgaC developers wanted :)

The open source FpgaC project is looking for a few more developers in various technology areas and skill levels. One pr...
13 comments posted 20yrs
posted by fpga_toys
13 comments posted 20yrs posted by fpga_toys

FSL to VHDL interface

Hello, I'm having great difficulty interfacing my FSL to my external (from microblaze point of view) VHDL. I want an FS...
9 comments posted 20yrs
posted by dale.prather
9 comments posted 20yrs posted by dale.prather

Xilinx ISE DRC: An antenna found

Hi all, After I use Xilinx ISE do Place & Round and generate bit file, I am confused with a DRC warning=E3=80=82 "WARNI...
1 comments posted 20yrs
posted by zhushenli
1 comments posted 20yrs posted by zhushenli

Stratum4E holdover

I'm working on a CT-bus (H100) implementation. Can I use the SPARTAN3E DCM to (help to) generate the HOLDOVER capabilit...
12 comments posted 20yrs
posted by oen_no_spam
12 comments posted 20yrs posted by oen_no_spam

problem with IO in EDK 8.1

Hi I want to use a networkmodule of Digilent and I downloaded a VHDL file from there website. => http://digilentinc.com...
5 comments posted 20yrs
posted by michiel.vanderlinden
5 comments posted 20yrs posted by michiel.vanderlinden