Latest threads in Field-Programmable Gate Arrays

interesting note -- altera C to hardware :)

http://www.fpgajournal.com/articles_2006/20060404_nios.htm

3 20yrs

fpga_toys

3 20yrs fpga_toys

Dual-edge synthesizable D flip-flop - any pitfalls?

Ralf Hildebrandt has described a dual-edge D-FF in his March 28th post - one page PDF is available at http://www.ralf-h...

4 20yrs

peter

4 20yrs peter

Source-synchronous IO constraints in Synplify

Does anybody know how to do source-synchronous I/O constraints in Synplify? (That get forwarded to the Xilinx backend t...

0 20yrs

jeremy

0 20yrs jeremy

How does the DCM phase shifting circuitry work? Xilinx Spartan 3

Essentially I need to know, for any given DCM configuration, how much the DCM outputs will shift in phase for each time...

21 20yrs

hyarbr01

21 20yrs hyarbr01

Streamlining FIRs in System Generator

Hello, I'm working on an FPGA implementation of a digital reciever. I decided to use Xilinx's Systen Generator for MATL...

2 20yrs

ithorpe

2 20yrs ithorpe

Lattice ispLever Starter Download

Hello friends, It appears that I can't download ispLever. I get a message that file isn't available. Is it working at Yo...

2 20yrs

prase.ruzicasto

2 20yrs prase.ruzicasto

Altera Stratix II GX LVDS max speed

I had spoke with Charley Pryor at Altera a few months back and had asked about running a 16-bit data bus into a Stratix...

8 20yrs

lecroy7200

8 20yrs lecroy7200

ISE under 64-bit Linux?

Just got an Athlon64 system. I want to be able to run the Xilinx ISE tool suite on this box under Linux. I'd also like...

4 20yrs

ptkwt

4 20yrs ptkwt

HDL Options @ EDK

Hello, Recently I bought an Ethernet Module from your web-site. I have used the recommended vhdl file (dpimref.vhd) to...

0 20yrs

michiel.vanderlinden

0 20yrs michiel.vanderlinden

System Ace

Hello: I have been using system ACE Compact Flash for configuration with a V2PRO system. I saw that one can use a micro...

0 20yrs

emh203

0 20yrs emh203

about the low power design

Can some have the material ahout the power design in fpga,and how to estimate the power in fpga,as I know the flash bas...

9 20yrs

bjzhangwn

9 20yrs bjzhangwn

XUPV2P

Hi, I have just received the XUPV2P board and trying to install the adept software to program it but the problem I seem...

1 20yrs

paul.sw.lee

1 20yrs paul.sw.lee

xilinx legacy input error

Hi folks, I have to speed up configuration of 2 FPGAs on existing board Virtex2Pro VP20 (master) S3-4000 they are wired...

0 20yrs

Antti.Lukats

0 20yrs Antti.Lukats

How fast is YOUR ise8.1?

I start to wonder if there is something weird with my design. I use a spartan 3 (4k), vhdl, and I suspect the synthesiz...

2 20yrs

mleikvol

2 20yrs mleikvol

Cheap Spartan 3 PCI express starter kit

Hi, I just saw the following article that claims that Xilinx has unveiled a PCI Express starter kit based on Spartan-3...

3 20yrs

ehliar

3 20yrs ehliar

Field-Programmable Gate Arrays

Worth reading in Field-Programmable Gate Arrays