Field-Programmable Gate Arrays

Dual-edge synthesizable D flip-flop - any pitfalls?

Ralf Hildebrandt has described a dual-edge D-FF in his March 28th post - one page PDF is available at http://www.ralf-h...

4 comments posted 20yrs

posted by peter

4 comments posted 20yrs posted by peter

Source-synchronous IO constraints in Synplify

Does anybody know how to do source-synchronous I/O constraints in Synplify? (That get forwarded to the Xilinx backend t...

0 comments posted 20yrs

posted by jeremy

0 comments posted 20yrs posted by jeremy

How does the DCM phase shifting circuitry work? Xilinx Spartan 3

Essentially I need to know, for any given DCM configuration, how much the DCM outputs will shift in phase for each time...

21 comments posted 20yrs

posted by hyarbr01

21 comments posted 20yrs posted by hyarbr01

Streamlining FIRs in System Generator

Hello, I'm working on an FPGA implementation of a digital reciever. I decided to use Xilinx's Systen Generator for MATL...

2 comments posted 20yrs

posted by ithorpe

2 comments posted 20yrs posted by ithorpe

Lattice ispLever Starter Download

Hello friends, It appears that I can't download ispLever. I get a message that file isn't available. Is it working at Yo...

2 comments posted 20yrs

posted by prase.ruzicasto

2 comments posted 20yrs posted by prase.ruzicasto

Altera Stratix II GX LVDS max speed

I had spoke with Charley Pryor at Altera a few months back and had asked about running a 16-bit data bus into a Stratix...

8 comments posted 20yrs

posted by lecroy7200

8 comments posted 20yrs posted by lecroy7200

ISE under 64-bit Linux?

Just got an Athlon64 system. I want to be able to run the Xilinx ISE tool suite on this box under Linux. I'd also like...

4 comments posted 20yrs

posted by ptkwt

4 comments posted 20yrs posted by ptkwt

HDL Options @ EDK

Hello, Recently I bought an Ethernet Module from your web-site. I have used the recommended vhdl file (dpimref.vhd) to...

0 comments posted 20yrs

posted by michiel.vanderlinden

0 comments posted 20yrs posted by michiel.vanderlinden

System Ace

Hello: I have been using system ACE Compact Flash for configuration with a V2PRO system. I saw that one can use a micro...

0 comments posted 20yrs

posted by emh203

0 comments posted 20yrs posted by emh203

about the low power design

Can some have the material ahout the power design in fpga,and how to estimate the power in fpga,as I know the flash bas...

9 comments posted 20yrs

posted by bjzhangwn

9 comments posted 20yrs posted by bjzhangwn

XUPV2P

Hi, I have just received the XUPV2P board and trying to install the adept software to program it but the problem I seem...

1 comments posted 20yrs

posted by paul.sw.lee

1 comments posted 20yrs posted by paul.sw.lee

xilinx legacy input error

Hi folks, I have to speed up configuration of 2 FPGAs on existing board Virtex2Pro VP20 (master) S3-4000 they are wired...

0 comments posted 20yrs

posted by Antti.Lukats

0 comments posted 20yrs posted by Antti.Lukats

How fast is YOUR ise8.1?

I start to wonder if there is something weird with my design. I use a spartan 3 (4k), vhdl, and I suspect the synthesiz...

2 comments posted 20yrs

posted by mleikvol

2 comments posted 20yrs posted by mleikvol

Cheap Spartan 3 PCI express starter kit

Hi, I just saw the following article that claims that Xilinx has unveiled a PCI Express starter kit based on Spartan-3...

3 comments posted 20yrs

posted by ehliar

3 comments posted 20yrs posted by ehliar

xilinx xc2vp30

Hi Iam planning to port leon (open-source processor) in xilinx virtex-II chip, bypassing power PC. Still May it be poss...

1 comments posted 20yrs

posted by prakash.na

1 comments posted 20yrs posted by prakash.na