Ralf Hildebrandt has described a dual-edge D-FF in his March 28th post
- one page PDF is available at
I'd like to hear opinions on the reliability of this circuit - can anyone see any issues with using this circuit.
PeterC.
If you have to do it to save power, that's as clean a way as any. If you don't have to, just double the clock rate and use the standard tools of synchronous design.
The main downside to dual-edge clocking is the new sensitivities added to static timing analysis. These include clock duty cycle and Tcq differences between the rising and falling flops.
-- Mike Treseler
This looks like the circuit that Gabor posted last May. It should work just fine.
Bob Perlman Cambrian Design Works
It is the same circuit, but why are two of the three XOR gates drawn as 2-input multiplexers with an iverter? This doesn't help me visualize the circuit at all...
Two people - one idea. Sorry, I did not know, that you posted a similar circuit - I have done it months ago, too. ;-)
It is only because I think it is more readable and may help to understand the idea. I am certain the synthesis tool will choose the best way of implementation.
Ralf
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