Hello,
Recently I bought an Ethernet Module from your web-site. I have used the recommended vhdl file (dpimref.vhd) to test this Ethernet Module. I placed the code that is used for the leds and buttons in comment because they are not available on the Ethernet Module.
When I download this design to a Xilinx Virtex II pro development board and I use the communication software from you web-site the communication doens't always go without errors.
The writing to the FPGA works perfect, but when I want to read from the FPGA sometimes I read out the address of the register where I want to read instead of the data of that register
Example: I write to the FPGA at register 0x01 the value 0x08. When I want to read from register 0x01 I read 95% of the times 0x08 but the other 5% I read out 0x01 with is the address.
I have asked the suport of digilent inc what I can do about this and they repleyed Before building the Dpimref logic in ISE: 1. In Project Navigator, right-click on "Synthesize-XST" (in the Process View Tab) and select "Properties" 2. Click the "HDL Options" tab 3. Set the "FSM Encoding Algorithm" to "None"
This is the trick when I use ISE but where can I set this option in the EDK?
Greets Mich