xilinx legacy input error

Hi folks,

I have to speed up configuration of 2 FPGAs on existing board Virtex2Pro VP20 (master) S3-4000 they are wired only for serial config, to 64 macrocell PLD with connection to MMC card and Atmel Dataflash the PLD has also 12MHz clock.

I assumed the fastest way of config would be using VP20 as master serial, setting config clock option to 26MHz and.. well doesnt seem to work

at first I tried config from MMC card, by using 2 bitstremeams

'appended' eg vp20.bit + s3.bit this works so that both FPGAs release DONE but only VP20 releases GWE, the S3 stays in configured but not-started state.

after using bitgen to embedded the s3 bitstream S3 also started to set GWE and both FPGAs configure ok and will become functional

this same bitstream also works when used from dataflash while VP20 is in master serial mode with cfgclock = 4MHz

as soon I as set the cfg clock option to anything higher then 4 (8 Mhz) then S3 still releases done, but VP20 sets "legacy input error" bit in status register.

I cant belive that 8MHz is too fast for VP20 in master serial mode, so where is the trick? the slave FPGA that is getting passthrough data from VP20 does configure OK so I assume the signal integrity isnt the problem, also I would rather expect CRC error when the VP20 would see corrupted data?

Any idea? new PCB isnt an option - the boards are made and are also somewhat functional the question is what can be done to get the serial clock boosted up

Antti

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Antti
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