Essentially I need to know, for any given DCM configuration, how much the DCM outputs will shift in phase for each time I nail PSINCDEC. I'm thinking that if I understand better how the PS part of the DCM circuit works I can answer this for myself. I've got a case in with Xilinx but either they're not understanding my question, or they're not sure how to answer, or who knows. Any help would be greatly appreciated. Here's the correspondence so far:

---------------------- Me: I'm using some DCMs in dynamic phase-shift mode in a Spartan 3 and I'm trying to understand how the granularity of each dynamic phase shift is tied to the period of CLKIN. Does the phase shift feature use a fixed tap delay? If so, the phase shift granularity would not be dependent on the period of CLKIN. Also, after reading XAPP462 I surmised that the longer the period of CLKIN (slower the CLKIN frequency) the less number of effective phase shift steps. This seems counter-intuitive. Can you help me to understand how the dynamic phase shifting is implemented in the DCM?

----------------- Xilinx: Craig, The DCM can always delay ~10ns. When your clock period is slower than ~100Mhz (10ns period), you will not be able to phase shift the full360 degrees. Additionally for slower frequencies, taps are combined as per XAPP462, such that you may not have 256 tap changes, but will still have 10ns of delay to work with. It's a little confusing, but the circuitry basically does not allow the same resolution at slow speeds as it does at high. Hope this clears things up.

------------------ Me: Thanks for your very quick response. I'm beginning to understand a little better. The goal is for us to know, for any given DCM config, how much dynamic phase shift occurs each time we nail PSINCDEC. For a DCM that has a max shift of 10ns and 512 steps or taps, is it safe to say that each tap is about 20ps? I understand that for slower CLKIN frequencies the taps could be combined to give 40ps, 60ps, etc. per step, and thus you'd have less than 255 steps in either direction. Is there a way to tell if the DCM we're using is combining taps, and how many taps per step? Thanks!

------------------- Xilinx: Craig, There will never be 512 taps, there are max 256 and each is around

40ps. The weight of each unit of increment will depend on the frequency of clk in. This is where XAPP462's equations come in. Sounds like you got it from there.------------------------ Me: No not quite. The 512 taps/steps I got from equation 4 (pg 42), where TCLKIN is less than 10 ns and the phase shift limits are +/-255. However that's for fixed phase shifting. For variable phase shifting there's 256 taps/steps when the shift limits are +/-128. Still, are you sure there's only 256 taps in the delay line, since there's +/-255 steps available in fixed phase shifting?

Also, if CLKIN is 250MHz and I step PSINCDEC once, will the output clock shift in phase by 40ps (or one tap delay)? What if CLKIN is

300MHz and I step once, will the output clock shift in phase by the same 40ps, or some multiple? Here I'm still confused as to how each unit of increment is tied to the frequency of CLKIN. Equation 9 (pg 45) doesn't hold true.--------------------