Field-Programmable Gate Arrays

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xilinx xc2vp30

Hi Iam planning to port leon (open-source processor) in xilinx virtex-II chip, bypassing power PC. Still May it be poss...
1 comments posted 20yrs
posted by prakash.na
1 comments posted 20yrs posted by prakash.na

Want HiSpeed USB on your FPGA ?

This new device from Philips claims USB 480MBd (+PHY), 1MB FLASH, and an ARM7 core - for $7.99/10K http://www.standardi...
1 comments posted 20yrs
posted by no.spam
1 comments posted 20yrs posted by no.spam

why the best code are the random codes ?

1- why the best code are the random codes ? 2- what is the difference between LDPC codes and other linear codes ?
1 comments posted 20yrs
posted by shereen.ahmed
1 comments posted 20yrs posted by shereen.ahmed

Xilinx XST incremental synthesis tooo slow

Hi! I was investigating incremental synthesis to reduce synthesis time. Bad surprise was that incremental synthesis doe...
0 comments posted 20yrs
posted by laurri
0 comments posted 20yrs posted by laurri

DMA with EDK

Hi! I unsuccessfully tried to find information about Direct Memory Access trough EDK. I would like to start by creating...
1 comments posted 20yrs
posted by louis.dupont
1 comments posted 20yrs posted by louis.dupont

embedded design prototyping

Hi all, Iam trying to develop an embedded mp3 player. I compiled...and installed in linux(FC4) + pentium platform. Now...
1 comments posted 20yrs
posted by prakash.na
1 comments posted 20yrs posted by prakash.na

Virtex-4 readback via ICAP

I am trying to perform readback of the configuration for a Virtex-4. I followed the steps in the configuration guide, b...
5 comments posted 20yrs
posted by 4mjunkee
5 comments posted 20yrs posted by 4mjunkee

Spartan3E data sheets

The newest version (3.0) of the Spartan3E complete data sheet came out a week or two ago. I just wanted to give my Kudo...
1 comments posted 20yrs
posted by johnhandwork
1 comments posted 20yrs posted by johnhandwork

Looking for chebychev equation

Hello all, I am looking for the equations used in the calculations of the coeffcients of chebychev IIR (2nd order) low...
7 comments posted 20yrs
posted by rover8898
7 comments posted 20yrs posted by rover8898

Spartan 3E SPI Programming

Hello I was reading through XAPP445 (SPI Configuration), on page 9 an indirect method of programming the SPI configurat...
3 comments posted 20yrs
posted by emh203
3 comments posted 20yrs posted by emh203

virtual slot implementation

Hello Groups, We have aggregate and segregate datas from two processor in FPGA.So we will have to snooping the data so...
0 comments posted 20yrs
posted by praveenkumar.bm
0 comments posted 20yrs posted by praveenkumar.bm

Problem erasing EEPROM XCF08P

I have installed a XCF08P EEPROM in my fpga board. The first time i wrote a program to it, it worked fine. But I can no...
4 comments posted 20yrs
posted by mughat
4 comments posted 20yrs posted by mughat

Inferring RAM with FOR loop

Hi all, I have written a simple code where data from a matrix(2-D array) is Xored with single dimensional array. On syn...
1 comments posted 20yrs
posted by vedpsingh
1 comments posted 20yrs posted by vedpsingh

Xilinx Kernel

Hello All, Any of you have ever used Xilinx Kernel in any project. I am wondering how easy its is to use. I am planning...
0 comments posted 20yrs
posted by fpgalearner
0 comments posted 20yrs posted by fpgalearner

wireless and bus

two wireless and bus forums www.buswares.com www.rdfwt.com browse after register
0 comments posted 20yrs
posted by water9580
0 comments posted 20yrs posted by water9580