Field-Programmable Gate Arrays

ISE 8.1 Sub module Synthesis

Hello: I ran into an issue (which may be a 'feature') in version 8.1 of ISE. When I have a simple verilog project with...

3 comments posted 20yrs

posted by emh203

3 comments posted 20yrs posted by emh203

Xilinx ISE Project Navigator bug

Hello all, I am running Xilinx ISE Project Navigator 8.1.03i. There seems to be an intermittent "bug"/"problem" that ke...

1 comments posted 20yrs

posted by rover8898

1 comments posted 20yrs posted by rover8898

comp.arch.reconfig

I'd like to canvass opinion here. I'm sure opinions will vary greatly. The question is: Is is time to create a new grou...

7 comments posted 20yrs

posted by robin.bruce

7 comments posted 20yrs posted by robin.bruce

regarding memories using megafunction wizard(altera)

Hi all, i am currently working on altera FPGAs,when i was trying to generate a memory using megafunction wizard,in the...

2 comments posted 20yrs

posted by bachimanchi

2 comments posted 20yrs posted by bachimanchi

Xilinx EDK 8.1 DDR controller behavior

Hi does anyone know what should happen on read access to DDR memory space when external connections to DDR memory are n...

3 comments posted 20yrs

posted by Antti.Lukats

3 comments posted 20yrs posted by Antti.Lukats

Supply Quick Color Pcb Prototype !(CHINA)

Supply Quick Color Pcb Prototype ! +silk+mask price is same. if any question, please send mail us!!!!!! Sell high quali...

0 comments posted 20yrs

posted by njbp188

0 comments posted 20yrs posted by njbp188

ISE 8.1i for Linux ?

Hello, at the moment I own a Spartan 3 experimentation board (from digilent) (the so called "Spartan 3 starter kit") th...

8 comments posted 20yrs

posted by jboehm

8 comments posted 20yrs posted by jboehm

How to avoid this waring in ISE 8.1?

When I complied any project with ISE 8.1 webpack with SP3, I got warnings like below: WARNING:ProjectMgmt - "G:/test/wa...

5 comments posted 20yrs

posted by springzzz

5 comments posted 20yrs posted by springzzz

Microblaze & Linux tools.

As of today, could anyone tell me: 1) Are Xilinx tools for FPGA design, especially microblaze, actually, solid, good, u...

8 comments posted 20yrs

posted by afc4

8 comments posted 20yrs posted by afc4

Tcl used in Modelsim?

Hi all, I am new to Modelsim and always use GUI to do all the work. I heard that we can use Tcl to control Modelsim to...

1 comments posted 20yrs

posted by zhushenli

1 comments posted 20yrs posted by zhushenli

altera async fifo with different read/write port widths?

Does anyone know if Altera has any prebuilt async fifo with different read/write ports? I am trying to target Cyclone d...

1 comments posted 20yrs

posted by fpgabuilder-groups

1 comments posted 20yrs posted by fpgabuilder-groups

XST pre-defined macros

All- Does XST provide any pre-defined macros or constants? For example: __BUILD_NUMBER __XST_VER that could be used in...

0 comments posted 20yrs

posted by jbrower

0 comments posted 20yrs posted by jbrower

Why Edge is required to read from Block RAM of V4

Hello all, Why xilinx is using edges to read from block RAM. That wont be a problem in most cases. But i am trying to i...

4 comments posted 20yrs

posted by vssumesh_asic

4 comments posted 20yrs posted by vssumesh_asic

More Xilinx S/W problems... ISE won't start

I installed SP3 for ISE 8.1 (webpack) yesterday and used it for a bit. I then ran a multi-pass P&R, then, when it was d...

3 comments posted 20yrs

posted by johnp3+nospam

3 comments posted 20yrs posted by johnp3+nospam

CAM, TCAM in Stratix

Hi, I am working on a 10 Gb Ethernet project (deep packet inspection) and nee to implement CAM in my FPGA. I am using a...

10 comments posted 20yrs

posted by freechip

10 comments posted 20yrs posted by freechip