How to avoid this waring in ISE 8.1?

You're not alone. I get this warning, too. And I don't know what it means or how to avoid it either!

-Dave Pollum

If you have an include file with a verilog module (stopwatch) then every time you reference that include file it will see that a module of that name has already been defined. It may be that an identical implementation will give a warning while a different implementation will give an error or at least a different warning. This all may also apply to VHDL.

John; This is the warning message I get when running a VHDL project using ISE

8.1SP3: "..MON_v3.NGR line 0 duplicate design unit: Module|Mon_v3", where "MON_v3" is my top VHDL module. I also have 2 lower level modules. I built a very similar project with no errors/warnings when I used ISE 7.1SP4.

I tried seaching for "duplicate design unit" on Xilinx's web site, but didn't find the warning. Would this be suitable for a web-case?

-Dave Pollum

I'd expect unexplained/undocumented errors and warnings would each warrant a web case. I haven't run VHDL through XST - I'm a Verilog guy in Synplicity tools.

Would it be safe to say you don't use include files (at least ones that reference the modules)? If you don't use them, the "duplicate" arrangement I envisioned wouldn't be an issue.

I have a nice test project that uses only one VHDL file with the description of a dual ported RAM. It gives that warning too. In fact

*every* VHDL project I have gives that warning.

Best regards,

Zara

PS: I never gave it more than five seconds thought, because I am more worried by the hundreds of unavoidable warnings given by a project containing an XPS/microblaze module.