altera async fifo with different read/write port widths?

Does anyone know if Altera has any prebuilt async fifo with different read/write ports? I am trying to target Cyclone device. The M4K blocks do allow variable width read/write ports but I cannot see any fifos made using those.

TIA

Reply to
fpgabuilder
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Try the lpm_fifo MegaWizard function. You can use separate read and write ports that are driven from two different unsynchronized clocks.

Reply to
Rob

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