Field-Programmable Gate Arrays

XST duplicate register option does not work

I have an application that has 300 pins on a tri-stated bus. They have a tight offset constraint for the output time. D...

1 comments posted 20yrs

posted by brannonking

1 comments posted 20yrs posted by brannonking

Xilinx Map & Physical Synthesis dies...

I've not ever been successful using the Xilinx Map options that use Pysical Synthesis. I've tried it with several versi...

2 comments posted 20yrs

posted by johnp3+nospam

2 comments posted 20yrs posted by johnp3+nospam

XILINX : IBIS model creation

Hi, I am using xilinx ISE 8.1 webpack version.In my design i have used spartan2,xc2s200 fg256 family of FPGA.After rout...

0 comments posted 20yrs

posted by mohan.kulkarni

0 comments posted 20yrs posted by mohan.kulkarni

Using another crystal oscillator..

Dear all of my friends, I need help please... Can I using another crystal oscillator instead of using SG8002DC / SG8002...

1 comments posted 20yrs

posted by aan.woodz

1 comments posted 20yrs posted by aan.woodz

Video circle generator

I would like to use a FPGA to create some simple test patterns. One of which is a circle with a variable diameter. I'm...

7 comments posted 20yrs

posted by fred

7 comments posted 20yrs posted by fred

is Rocket io complaient with IEEE 802.3ae standard

I am trying to connect rocket io with yet another ASIC, which send out data that are compliant with IEEE 802.3ae standa...

0 comments posted 20yrs

posted by syshen

0 comments posted 20yrs posted by syshen

Bluetooth with FPGA?????

hi everybody, I am in the last year of communications department, faculty of Engineering, and I need help for my gradua...

4 comments posted 20yrs

posted by aymmmm

4 comments posted 20yrs posted by aymmmm

Raggedstone1 and Opencores PCI

We think we have got to the bottom of the issues that some of you had with Opencore PCI designs had with our Raggedston...

0 comments posted 20yrs

posted by removethisthenleavejea

0 comments posted 20yrs posted by removethisthenleavejea

problem with shift operation

I hav the follwoing simple code which does left shifting operation. library IEEE; use IEEE.std_logic_1164.all; use IEEE...

1 comments posted 20yrs

posted by Chandru.Kundagol

1 comments posted 20yrs posted by Chandru.Kundagol

Initializing array of BlockRAM instances in verilog

Hi, I'm trying to create an array of Virtex-II BlockRam instances in verilog using RAMB16_S36_S36 BRAM[ram_modules-1:0]...

5 comments posted 20yrs

posted by allanca

5 comments posted 20yrs posted by allanca

Editing Spartan3 DCM in FPGA(8.1.03) editor

Whenever I try to change something in a DCM, a non-reversible error appears in DRC. All the unused pins on the DCM is s...

3 comments posted 20yrs

posted by mleikvol

3 comments posted 20yrs posted by mleikvol

How to trsiate o/p pins?

Hi, I am new to designing with FPGAs. I have an enable_output pin in my FPGA which if deasserted will make the o/p data...

2 comments posted 20yrs

posted by g.shrinivasan

2 comments posted 20yrs posted by g.shrinivasan

cheapest board (of any sort) with an Atmel At94k40 FPSLIC on it?

Hi, I'm interested in doing some experiments requiring a rather large number of Atmel At94k40 chips (or, in a pinch, At...

0 comments posted 20yrs

posted by megacz

0 comments posted 20yrs posted by megacz

An experience with Xilinx 8.1.02i

Hi, I would like to share with you my an experience with error generation when inconsistant Xilinx Navigator 8.1.02i se...

0 comments posted 20yrs

posted by wtxwtx

0 comments posted 20yrs posted by wtxwtx

fpga space estimate

Hello all, I would like some feeback : I am planning to make a design in FPGA that has 4 2nd-order cascaded IIR filters...

7 comments posted 20yrs

posted by rover8898

7 comments posted 20yrs posted by rover8898