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Why Edge is required to read from Block RAM of V4

Hello all, Why xilinx is using edges to read from block RAM. That wont be a problem in most cases. But i am trying to implement the 16 port read/wrte RAM by a method suggested in an earlier post. The RAM is constructed with lot of individual RAM units. And in this there is a need to write to a RAM with input data XOred with data from other RAMs. But if we need an edge to read from the memory content this is not possible. Other method is to use +ve edge for reading and negedge for writng. But this is also not possible because there is one more read is required in the same cycle. Any comments. regards Sumesh V S

Reply to
vssumesh
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A 16 *port* RdWr memory requires the equivalent of about 256 BlockRAMs. You sure about this? Do you mean 16 entry?

Reply to
John_H

I do not understand your design, but take my word for it: Reading the Xilinx BlockRAM content absolutely requires a clock edge. Nothing happens in the address decoder without a clock edge. In many cases this is a desirable feature, in some cases it is not desirable, but it is a fact: You need a clock, not only for writing, but also for reading. Peter Alfke, Xilinx Applications

Reply to
Peter Alfke

Hello John_H, Thank you very much for your idea. It saved almost 20K LUTs. Actually i want a circuit equivalent to 16 port RAM. But as you pointed is not avilable in lx60. What i am thinking now is to time multiplex the full operation. 8 port first then the next eight ports. This will need only 64 RAMs. Thank you once again for your brilliant idea. regards Sumesh V S

Reply to
vssumesh

bad news...... will use multiplied clock for extra edge requirement..... regards Sumesh

Reply to
vssumesh

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