comp.arch.reconfig

When this newsgroup is overloaded with postings regarding reconfigurable computing, such a new group might be indicated.

-- Mike Treseler

Hi Robin, Interestingly enough, I believe this group started off with this charter:-

CHARTER

The unmoderated newsgroup comp.arch.fpga will be open to discussions on all topics related to the use of reconfigurable Field Programmable Gate Arrays (FPGAs) as computational engines.

see:-

That's why it's in the comp. hierarchy.

Perhaps you should complain about all the non-computing folks spamming your newsgroup? :-)

Cheers, Syms.

John Williams started a partial-reconfig-mailing list a few years back:

You can find the list archives here:

Traffic is moderate, but I believe most active "reconfigurators" read it and post there regularly. I think this list is "the place to be" when you're doing something with partial reconfig at the moment.

cu, Sean

Actually, all the electrical engineering design questions, and FPGA product support questions here are probably off topic, as this forum was SUPPOSED to be about FPGA computing, not hardware design and FPGA VHDL/Verilog design support questions.

Maybe what needs to happen, is creating an FPGA hardware design forum some place else for the hardware designers and FPGA vendors product support discussions?

I suppose it would make sense to change the charter of this newsgroup to reflect usage. Joking aside, c.a.f pretty well reflects how the majority of FPGAs are actually used, so I wouldn't make the case that there's anything wrong with the group. I suppose I believe that there's more interest in reconfigurable computing than is being suggested by the volume of posts here. Maybe the best thing for me to do in the short run is to try and start up a few reconfigurable-computing posts here and see what happens.

Rob> Rob> > I'd like to canvass opinion here. I'm sure opinions will vary greatly.

Sean,

thanks for your post. Partial Reconfiguration is something that is of interest to reconfigurable computing as I understand it, but it's not something that anyone is putting on their critical path. Xilinx FPGAs are not currently designed with commercially-viable partial reconfiguration and the toolchains, although developing, are still not there. Dynamic reconfiguration is probably about as far as it goes for most people.

The best example of "reconfigurable computing" as I understand it at present is embodied by SRC computers. Their SRC-6 and SRC-7 machines tightly couple microprocessors to FPGAs and provide a development environment that balances a high-level of abstraction from FPGA design with high performance. Check out the performance stats for the SRC-7:

Cheers,

Robin

That's probably true, but somehow seems to defeat the sense of order that the usenet folks setup to catorgize topics/groups. There are other places for electronics, engineering, and product support for those.

Comp.arch just isn't the place for VHDL/Verilog training and support, particularly for vendor specific issues. Nor is circuit level design, interfacing, etc really an computer architecture topic for custom hardware. Even partial reconfiguration for most hardware projects, isn't on topic, although a related technology for this group.

SoC, reconfigurable computing, and even hardware designs for building fpga computers would be on topic for a comp.arch rooted group.