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Xilinx EDK 8.1 DDR controller behavior

Hi

does anyone know what should happen on read access to DDR memory space when external connections to DDR memory are not correct? I am troubleshooting a custom board and what I see is that OPB DDR controller makes total OPB bus freeze on first DDR read access. ToutSup=1 and then nothing happens. In the datasheet DQS strobe is going to WREN of read fifo so I could think a missing DQS from external chip could cause bus freeze, but I am not really sure as it is not described in the datasheet (eg what should happen on missing DQS).

I have tried all DDR controllers from EDK 8.1 PLB_DDR OPB_DDR OPB_MCH_DDR and all seem to have similar freeze behaviour the DCMs all work (tested) and the EDK system also works - well until first read to DDR space

any helpful hints?

Antti

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Antti
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Antti

When you get a timeout the OPB bus master should release the bus removing "SELECT" and other signals from active to their inactive state of all "0"s. I'm guessing the DDR module isn't passing back the XFERACK as expected.

If you have done this manually check the timeout signals are wired into the array correctly.

John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board.

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Reply to
John

It freeze ... ie, never acks the transfer.

We use the ddr controller from EDK (without any ipic/ipif, just the bare controller that's common to plb_ddr, opb_ddr & co) and if the phase shift of the second dcm is off, it never acks and thus freeze.

Sylvain

Reply to
Sylvain Munaut

thanks!

this is what I guessed too, just wanted confirmation that it really freezes when no DQS on reads are seen.

Antti

Reply to
Antti Lukats

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