Field-Programmable Gate Arrays

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FPGA : Constraint for BRAM placements

Hi want to know how to add Location constraint for BRAM placements in my design I am using a statement like this INST "...
1 comments posted 20yrs
posted by pbijoy
1 comments posted 20yrs posted by pbijoy

FPGA : P&R problem - Help !

Hi I am facing the following problem during P&R of my design =================================== Error - Description Ph...
3 comments posted 20yrs
posted by pbijoy
3 comments posted 20yrs posted by pbijoy

Verilog vs VHDL

Hi, I know this has been brought up many times in various groups but here is my view on them and I would really appreci...
28 comments posted 20yrs
posted by kishore2k4
28 comments posted 20yrs posted by kishore2k4

I2C on Xilinx V4

Well, I have a requirement for I2C or IIC communications to some video decoder chips on a new board I am designing. I w...
9 comments posted 20yrs
posted by bradsmallridge
9 comments posted 20yrs posted by bradsmallridge

.hex or .svf file from Mediatronix picoBlaze IDE

Hi, I am using Mediatronix picoBlaze to write assembly code for Xilinx picoBlaze and like to generate .hex or .svf file...
0 comments posted 20yrs
posted by nobody
0 comments posted 20yrs posted by nobody

PCI 64/66 fpga eval boards

Folks, After search the net for various eval boards, I haven't found the one that I need and afford... that is so oxymo...
20 comments posted 20yrs
posted by fpgabuilder-groups
20 comments posted 20yrs posted by fpgabuilder-groups

FPGA delay generator

Hello everybody, Currently I am designing very accurate delay generator, which will be based on FPGA . This delay gener...
12 comments posted 20yrs
posted by sinebrate
12 comments posted 20yrs posted by sinebrate

OPB Timer MicroBlaze

Has anyone used the OPB Timer on the MicroBlaze? I am trying to figure out how it works and by doing that I have inspec...
2 comments posted 20yrs
posted by raybakk
2 comments posted 20yrs posted by raybakk

ISE 8.1SP4 PN doesnt start

hi after deleting unused xilinx webpack directory the main ISE doesnt start anymore is there some trick except full re-...
10 comments posted 20yrs
posted by Antti.Lukats
10 comments posted 20yrs posted by Antti.Lukats

Xilinx -- please help with Virtex-4 datasheet

How does one, using the Virtex-4 datasheet, calculate IOB setup and hold time requirements and global clock-to-out time...
1 comments posted 20yrs
posted by nimby1_NEEDSPAM
1 comments posted 20yrs posted by nimby1_NEEDSPAM

ModelSim Designer

Is anybody out there actually using ModelSim Designer? We have a single license as well as 2 PE licenses. Today I could...
0 comments posted 20yrs
posted by sharpa17
0 comments posted 20yrs posted by sharpa17

i need glasses

Is not that just typical, it was laying in front of me all the time...
0 comments posted 20yrs
posted by thebestspirit
0 comments posted 20yrs posted by thebestspirit