Latest threads in Field-Programmable Gate Arrays

FPGA PCIe core connectivity w/ a PC

Hi, We want to the purchase the Xilinx PCIe IP core for a high speed serial link for use with the Xilinx ML321 V2pro de...

0 20yrs

ok

0 20yrs ok

Building a board with Spartan 3 FPGA.

Hi, I am trying to build a very simple Spartan3 - based FPGA board. The idea is to have FPGA + Flash PROM & Jtag header...

12 20yrs

interpasha

12 20yrs interpasha

xilinx pricing discrepancy

Can anyone explain why the quotes that we are getting from Xilinx are 4x their own marketing materials? For example thi...

15 20yrs

someone

15 20yrs someone

Independent clock FIFOs

Hi all, I am using a Virtex-II Pro in ISE 8.1i and have generated a couple of asynchronous FIFOs in Coregen. The data p...

9 20yrs

rob.misc

9 20yrs rob.misc

Urgent help programming SPI-flash trough JTAG (Spartan3E)

I need help to program the SPI-memory connected to a Spartan3E device. The memory is a M25P40. I already have the devic...

6 20yrs

bbb

6 20yrs bbb

incremental chip building in ISE

Hi, I am currently involved in a large FPGA project using Xilinx Virtex 2 pro devices. Building the FPGA from RTL can t...

0 20yrs

jayasanka.piyaratna

0 20yrs jayasanka.piyaratna

Unknown Processor Version (8)

Hi there When I try to start XMD for debugging I get the following error: Unknown Processor Version (8) and Verify if F...

3 20yrs

raybakk

3 20yrs raybakk

MicroBlaze and IIC

Hey I am trying to get familiar by using a I2C-bus to connect to some external components, i'm quite new to the Xilinx...

1 20yrs

thebestspirit

1 20yrs thebestspirit

[Xilinx V4SX55]DDR2 SDRAM controller + dual purpose pins

Hey, I'm using a V4SX55-FF1148 device and as framebuffer i have build a DDR2 controller ... now i'm having 2 of those c...

8 20yrs

tim.verstraete

8 20yrs tim.verstraete

How simple can FPGA design be? (Mission Possible 2006)

Some things are simple. Some things are fun. FPGA's are both Simple and Fun - for all the Family! Arent they? Even on S...

3 20yrs

Antti.Lukats

3 20yrs Antti.Lukats

Quartus ByteBlaster in Active Serial Programming mode not working

Hey folks I have an Elektor FPGA project board (with an Altera EP1C12k and a EPCS4). My board is working nicely, but I'...

3 20yrs

w.h.oami

3 20yrs w.h.oami

MicroBlaze as SubModule Problem

My Design Implements a MB processor, and in XPS I use "Tool - > Export to ProjNav" to export the processor to my design...

5 20yrs

hitsx

5 20yrs hitsx

Have someone implementate the cpu86 or sparc embeded processor in the v-2 fpga

I want to to get the hardware(pcb or shematic) or some other files,and also I want to know if I want to do this what sho...

6 20yrs

bjzhangwn

6 20yrs bjzhangwn

JTAG chaining of two different Xilinx Spartan 3E boards

Hi, I've two development boards with me. 1) Spartan 3E Sample Pack(XC3S100E) with a standard 6-pin JTAG connector 2) Sp...

2 20yrs

kishore2k4

2 20yrs kishore2k4

Signal 2 clocks long but only one clock possible

hello, in a design with virtex4 lx25-10 I have a problem which is caused by an effect I do not understand. I create chi...

7 20yrs

dennis.binder

7 20yrs dennis.binder

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