OPB Timer MicroBlaze

May 23, 2006 2 Replies

Has anyone used the OPB Timer on the MicroBlaze?



I am trying to figure out how it works and by doing that I have inspected some adresses:



in the xparameters.h #define XPAR_TESTTIMER_BASEADDR 0x41C00000



in the xtmrctr_l.h #define XTC_TCSR_OFFSET 0 /**< control/status register */ #define XTC_TLR_OFFSET 4 /**< load register */ #define XTC_TCR_OFFSET 8 /**< timer counter register */



After I have called the function XTmrCtr_mWriteReg(XPAR_TESTTIMER_BASEADDR, 0, XTC_TLR_OFFSET,



0x0F0F0F0F); I suspected the memory to look like this:


0x41C00000 00 00 00 00 00 00 00 00 0f 0f 0f0f 00 00 00 00



0x41C00010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

But however it looks like this. Does anyone know whats wrong?


0x41C00000 00 00 00 00 0f 0f 0f 0f 00 00 00 00 00 00 00 00
0x41C00010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

in the in the xtmrctr_l.h The function I am calling is defined like this: #define XTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite) \ XIo_Out32(((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + \ (RegOffset)), (ValueToWrite))



The XTmrCtr_Offsets[(TmrCtrNumber)] is "defined" ekstern extern Xuint8 XTmrCtr_Offsets[]; Where is it ? Do I need to include some other headers? I suspect it to be the reason that the memory looks unexpected.



Raymond



Hi Raymond,

Nothing is wrong, the memory looks perfect. The "TLR" register is 4 bytes above the base address and that's where the data got written. Why do you think the memory should look different? If you wrote to the XTC_TCR_OFFSET then it would look like what you "suspected" before... did you make a typo?

-Ben-

No Ben no typos this time.

This is my fault I counted from the left, not the right sorry.

But thanks for answering :)

Raymond

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