I'm having what appears to be an 'output drive strength' problem with some Micron DDR DRAMs (46V32M16). Specifically, it appears that the parts either are not able to drive SSTL-2 Class II nets or the power up behavior of the Micron device does not default to SSTL-2 Class II as it says in the specification. This behavior seems to be present when using 'newer' die revisions of the part. The particular board design uses an Altera Stratix II EP2S60 which in turn uses an Altera Megacore version 3.2.1 DDR Controller. The board design itself is SSTL-2 Class II for the DDR signals and has been working in the lab without problem for approximately 1 year using older die revision parts. I haven't been able to confirm on the actual board yet whether or not the Megacore's DDR Controller design performs a write to the 'Extended Mode Register' to overwrite the power up default value for the output drive strength or not, but in the simulation model it appears to write all 0 which is correct and should leave the drive strength at what is needed for Class II operation.
When I probe DQ0 during a read, the signal only moves between 0.96V and
1.54V with 'newer' die rev parts (Rev C and Rev F) but swings between-0.21V and 2.5V with an 'older' die rev part. The board design itself is SSTL-2 Class II and has been working without incident for approximately the past year. Now I'm testing the newer die revision parts and it is failing functionally. Poking around all the inputs doesn't seem to show anything amiss but when I look at the DQ and DQS pins during a read (i.e. when the Micron DDR is driving) I seem to see this same 'small' voltage swing.
I'm still trying to validate whether the Altera DDR controller is walking through the initialization sequence properly on the actual board but was wondering if anyone else had seen such stuff before.
Any suggestions?
KJ