Field-Programmable Gate Arrays

ppc instruction count

Hi, Can anyone tell me how I can count the number of instructions or cycles needed for a particular piece of code? Other...

5 comments posted 20yrs

posted by eascheiber

5 comments posted 20yrs posted by eascheiber

Is it Possible to generate VHDL code for DDR SDRAM using Mig1.5

Hello guys, I have a system FPGA in vhdl for the virtex board and would like to generate DDR controller . When i tried...

4 comments posted 20yrs

posted by subin.82

4 comments posted 20yrs posted by subin.82

ISE8.1 on OpenSUSE 64bit

Hi *, just installed ISE8.1 with SP3 on a 64bit Linux-machine running OpenSUSE 10. Just thought I'd give it a try, even...

7 comments posted 20yrs

posted by smd

7 comments posted 20yrs posted by smd

Efficient implementation of Address Decoding logic

Hi all, I am using 6.3.02i Xilinx editor and Modelsim 5.3 simulator. I am slightly confused about which type of address...

10 comments posted 20yrs

posted by bj.srikanth

10 comments posted 20yrs posted by bj.srikanth

FlipChip BGA Conformal Coating

Xilinx app note XAPP426 v1.3 (March 2006) indictes that: "Xilinx has no experience or reliability data on flip-chip BGA...

10 comments posted 20yrs

posted by no-spam

10 comments posted 20yrs posted by no-spam

Re: Jtag Programmer

Forgot the message :) Anyone know of a decent FPGA/Prom Jtag programmer for Xilinx FPGAs? Thanks, Colin > >

3 comments posted 20yrs

posted by colinhankins

3 comments posted 20yrs posted by colinhankins

ISE Timing Analysis Misreporting? Bug?

Ok, so I'm working with a COTs DSP board vendor's ISE project and customizing the logic (essentially tossing code in a...

3 comments posted 20yrs

posted by killerhertz

3 comments posted 20yrs posted by killerhertz

Xilinx Floorplanner basic question

Hi all, I have to admit I have never used the floorplanner before for anything useful. I am looking at a partially rout...

0 comments posted 20yrs

posted by mbmsv

0 comments posted 20yrs posted by mbmsv

ProjectMgmt WARNING from ISE 8.1i XST

At the end of a successful synthesis (according to XST), I keep getting this warning: WARNING:ProjectMgmt - "C:/

1 comments posted 20yrs

posted by marcoa.castellon

1 comments posted 20yrs posted by marcoa.castellon

Webpack larger than CDs

I don't know exactly when this happened, but webpack will no longer fit on a single CD. I seem to recall when they spli...

18 comments posted 20yrs

posted by spamgoeshere4

18 comments posted 20yrs posted by spamgoeshere4

The simulation of Xilinx DDC(Digital Down Convert) IP Core can't gain the result

Hi,everyone i want to use the Xilinx DDC core version1.0, so i must simulate it by modelsim,but i found the result of R...

0 comments posted 20yrs

posted by mlpei279

0 comments posted 20yrs posted by mlpei279

Jumps in Reading out

Hello, How to explain the difference of the following two cases? I thought that case one should be better, but the read...

0 comments posted 20yrs

posted by tanceqi

0 comments posted 20yrs posted by tanceqi

MIL Qualified RTOS for PowerPc 405

Hallo, which RTOS have been MIL-Qualified to run on PowerPc 405 (in Virtex-4 FX)? Many Thanks Marco Toschi

5 comments posted 20yrs

posted by marc

5 comments posted 20yrs posted by marc

Help on DDR SDRAM contoller generated by MIG1.5

Hello guys, Is anyone used the Mig tool to generate a DDR SDRAM controller here.i have some doubts on the code generate...

5 comments posted 20yrs

posted by subin.82

5 comments posted 20yrs posted by subin.82

How to use usb on Alter EPXA4??

Hi,all: I want to use webcam to capture image data by using usb1.1. Is it difficult to do? I am a flashman on it and st...

0 comments posted 20yrs

posted by j93005

0 comments posted 20yrs posted by j93005