Hello,
How to explain the difference of the following two cases? I thought that case one should be better, but the readout data sometimes have big jumps. It seems that case two can work better in my tests. Thanks!
CASE ONE:
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-- Read out data in FPGA to PC read_proc:process(clk) begin
if clk='1' and clk'event then if read_EN = '1' then case read_address is when xxx => read_port