Field-Programmable Gate Arrays

Asynchronous BRAM input ?

Hi I have a problem when synthesizing my implementation. I am implementing simple controller for sorting two arrays X={...

6 comments posted 20yrs

posted by pasacco

6 comments posted 20yrs posted by pasacco

Multi place and route

hi all, few days a go I updated my ISE8, now I have ISE Foundation 8.03i and the problem is when I want to perform a mu...

3 comments posted 20yrs

posted by mazouz.nezhate

3 comments posted 20yrs posted by mazouz.nezhate

Documentation miss? (sp3/xilinx)

In the Sp3 full datasheet p56/206 there's some notes numbered (3) and (4). They are not to be found below table 31. Is...

3 comments posted 20yrs

posted by pbdelete

3 comments posted 20yrs posted by pbdelete

partial reconfiguration protocol on Spartan II and self reconfiguration

Hello folk, I've been supervising a project on reconfigurable computing at my University whose objective is to create a...

0 comments posted 20yrs

posted by sec_lab

0 comments posted 20yrs posted by sec_lab

FPGA board for USB experiments?

Hi. I want to get my brain around USB interfaces, how to design the hardware and the software, and eventually to find w...

27 comments posted 20yrs

posted by DaveFarrance

27 comments posted 20yrs posted by DaveFarrance

VHDL code For Floating point adder and Multiplier

Dear all, I am implementing FLOATING point FIR filter with LATTICE structure. For this project i want 32bit Floating Po...

3 comments posted 20yrs

posted by mailmekaran

3 comments posted 20yrs posted by mailmekaran

Difference Logic Cells <=> Slices

Hi I have a question. What is the difference between Logic Cells and Slices on an FPGA? I have noticed that on the Virte...

2 comments posted 20yrs

posted by michiel.vanderlinden

2 comments posted 20yrs posted by michiel.vanderlinden

Xilinx ISE 7.1i Tutorial: Test Bench road block

Using Xilinx ISE 7.1i, service pack 4, IP update 3 Windows 2000 Pro Tutorial: "ISE Quick Start Tutorial" When creating...

2 comments posted 20yrs

posted by richgrise

2 comments posted 20yrs posted by richgrise

Adding a USB interface to Linksys WRT54G wifi router

Is it possible to add a USB interface to the WRT54G board (a Linksys broadband router)? I found the following schematic...

3 comments posted 20yrs

posted by be.geek

3 comments posted 20yrs posted by be.geek

Problem with Xilinx ISE 7.1i core generator

Looks like I have a few more hurdles before getting started with my Spartan 3e board. This time, I seem to be having tr...

1 comments posted 20yrs

posted by jshamlet

1 comments posted 20yrs posted by jshamlet

WebPack on Linux

Dear FPGA Pros, I have a problem installing WebPack on Linux. While Xilinx recommends RedHat, I would like to use one o...

5 comments posted 20yrs

posted by flx

5 comments posted 20yrs posted by flx

Changing the random seed in Xilinx tools

Hi, I would like to know if there is a away to change the random seed used by the Xilinx tools ? I would like to do this...

2 comments posted 20yrs

posted by the.gaffar

2 comments posted 20yrs posted by the.gaffar

Free Tools

For the academics out there we are please to announce an offer, in conjunction with our partners Synplicity(R) Inc., of...

0 comments posted 20yrs

posted by removethisthenleavejea

0 comments posted 20yrs posted by removethisthenleavejea

Simulating post par simulation model

Hello all, I am trying to simulate a post par simulation model of a design which contains block RAMs. The source code i...

5 comments posted 20yrs

posted by vssumesh_asic

5 comments posted 20yrs posted by vssumesh_asic

Delay or latency

Why system generator block accepts delay block with zero latency. I always thought latency is actually the delay if tha...

2 comments posted 20yrs

posted by fpgalearner

2 comments posted 20yrs posted by fpgalearner