FlipChip BGA Conformal Coating

Xilinx app note XAPP426 v1.3 (March 2006) indictes that: "Xilinx has no experience or reliability data on flip-chip BGA packages on board after exposure to conformal coating."

WTFO ?

How is it possible with Xilinx being so tight with Military developers that they haven't tested their parts under the conditions which nearly all military boards are produced?

What am I missing? Have they been sworn to secrecy? :-))

-BH

Reply to
bh
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bh,

We are actively working with many military contractors on packaging.

And, they have been tested, and they don't fare well. All our packages breath. If they get conformal coated, then any moisture inside is trapped. If they could bake before coat, potentially this works ... but the tests continue.

Then when the heat is on, they POP if they adsorbed any moisture (even through the coating).

This is not unique to Xilinx, but an industry wide problem with all flip chip packages today.

In the FPGA business we have the distinction of making the largest die in the industry.

In the lobby of the IDA building

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there area series of posters of pcbs. Center in many of them is a Xilinx FPGA. These posters caught many by surprise, as in most recent systems, there is a Xilinx FPGA. (Even the military had no idea how pervasive FPGAs have become)

Coatings are typically used where there is no protection from the environment at all. Many systems provide environmental protection at the box level.

There are some packages which are qualified for coating (hermetic), but they are either too small for our die, or they have not been qualified for our use, yet.

Aust> Xilinx app note XAPP426 v1.3 (March 2006) indictes that:

Reply to
Austin Lesea

The problem is that the boxes, while not having any air-flow in the box, do have pressure vents that allow air-pressure to adjust. In some cases (like boxes with PCMCIA cards) they even have drain holes to allow moisture and dust to 'drain'. Practically all of the systems I've seen recently (including those with FPGAs) have conformal coatings.

I suspect many do a 4-hour bake at 125C to force out any moisture before applying the conformal coat, which if the proper coating is used and applied properly should stop any moisture transfer.

How does the underfilling effect moisture venting?

-bh

Reply to
bh

These types of packages are a serious issue in our mil systems that we've been working for sometime. We have techniques that address the problem but keep looking for a real solution.

Sam

Aust> bh,

Reply to
se

Are you allowed to mention what the actual die size for something like a XC4VLX200 is? I would have tended to guess that the MPU people with

200mm^2 dice were at the higher end of the industry, except for the people who make camera sensors and are up to 900mm^2 of CCD.

Tom

Reply to
Thomas Womack

Conformal coating is not usually a sufficient moisture-mitigation technique on its own for equipment that has very long (decades) storage and/or operational requirements in severe environments. With so many devices available only in plastic, non-hermetic packages, many projects end up mitigating at the box level, which means completely sealed boxes, purged with dry air or nitrogen, and the use of dessicants based on the leak rates of the seals on the box.

However, conformal coating is often used, even in these sealed environments, as FOD (foreign object debris/damage) mitigation. It prevents debris that may come about because of vibration, age/decay, etc. from causing operational problems (like shorting out conductors).

Andy

Reply to
Andy

The top-end device in each of the Virtex families is larger than 20 mm x 20 mm, but smaller than 25 x 25 mm. So, we are talking about roughly

500 square mm of silicon, much larger than typical CPUs. Within each family, the area is roughly proportional to the part number. Thanks to careful design techniques, and superb processing at our foundries, we do get acceptable yield with these big chips. (BTW, Altera is in a similar situation. It's a competitive world).

Peter Alfke,Xilinx Applications

Reply to
Peter Alfke

bh,

The problem is even after bake, a conformal coat is not 100% moisture proof (adsorbs water).

We have seen conformal coated flip chip packages where the moisture gets inside and then corrodes things.

The underfill is 100% epoxy, so there is no concern with anything actually getting under the die itself.

Austin

Reply to
Austin Lesea

Thomas,

It is no secret now, as there are companies which tear the parts apart. I'll save you the $20,000 for buying their report.

The LX200 is close to reticle limited, which means that is is about 22 X

24 mm. Just shy of 500 sq mm.

At least one family member is always at this limit, as that is how we maintain "sir superiority." The 4VFX140 is also right about at that size.

That makes us at least 2x the size of any other commercial product. Most ASIC houses never make a die much larger than 10 X 10 mm, for example. If asked, their foundries can't yield anything that large, because they never have had to.

I have talked to the guys who make the 900 mm square (and larger) die. They get less than one die per 8" wafer. That kind of yield is obscene. Since they get $125,000 per die when they are done, they can afford to do this. That is one hell of a camera sensor, however.

Austin

Reply to
Austin Lesea

Many thanks: I'd googled and found the competitive analysis companies, but they clearly regard the device-size figure as being part of the meat of their report, and want you to buy the report before they mentioned it.

That makes a lot of sense; I presume that the reticles stay fairly similarly sized across generations, so the V5LX330 will be the same sort of physical size. The Intel Montecito processor is 27mmx22mm, which I suspect means Intel acquired machinery with a slightly larger reticle.

Astronomical sensors are really crazily priced:

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has a 13cm^2 chip, and costs the same as a new Ford hybrid car.

The Canon 5D has a 36x24mm sensor and costs about $3000; on the other hand, I imagine the yield for image sensors isn't so enormous an issue: provided the output circuitry is all there you can interpolate around single dud pixels. I don't know, and I'm sure this is something for which the competitive analysers would charge the earth, whether the routing circuitry in FPGAs has redundant paths selectible by fuse.

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is quite an interesting article about the issues involved with getting astronomical chips made. They're clearly using very different fabs from Chartered, UMC, TSMC and the other usual suspects - a CCD fab engineer was talking about the possibility of moving to six-inch wafers this year, whilst I get the impression that the big fabricators have been on 12" ones for a while.

Tom

Reply to
Thomas Womack

Who is "our" and "we"?

Reply to
fpga_toys

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