Field-Programmable Gate Arrays

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Need help reg Power Estimation using PowerPlay

Hi, My problem is as follows: I am trying to estimate the dynamic power of my Nios II based system using the PowerPlay...
0 comments posted 20yrs
posted by iluvmylife
0 comments posted 20yrs posted by iluvmylife

Xilinx ISE 8.1i Trouble

The VHDL source and UCF file are at the bottom of this document. The error that I'm getting is: NCD was not produced. A...
16 comments posted 20yrs
posted by alexmchale
16 comments posted 20yrs posted by alexmchale

FSM State Minimization on FPGAs

Hi everybody, after a long discussion about State Minimisation with ISE...
17 comments posted 20yrs
posted by nix
17 comments posted 20yrs posted by nix

Quartus 6.0 Fitter Critical Warning

I compiled my Design with the new version 6.0 of Quartus and get much more Warnings :-( Especially a Critical Warning o...
5 comments posted 20yrs
posted by manfred.balik
5 comments posted 20yrs posted by manfred.balik

Microblaze, -mxl-gp-opt and small data areas

The question is simple: Has anybody used small data areas from inside C/C++? I have been abel to use it frm within asse...
0 comments posted 20yrs
posted by dlm0-hbge
0 comments posted 20yrs posted by dlm0-hbge

Programmable clock ics8442

Hi, I have a memec V4-MB development kit.In it there is a programmable clock ics8442.I am trying to configure it,but no...
0 comments posted 20yrs
posted by subin.82
0 comments posted 20yrs posted by subin.82

Processor Design

Hello I am looking for good Tutorials which show how to implement a processor archtitecture for a FPGA. Also good tutor...
1 comments posted 20yrs
posted by ernte23
1 comments posted 20yrs posted by ernte23

Xilinx bitgen vs output file name

I'm using Xilinx 8.1 and would like to find a way to have bitgen create its output files with a different basename from...
1 comments posted 20yrs
posted by johnp3+nospam
1 comments posted 20yrs posted by johnp3+nospam

Aurora core example simulation

Hi, I'm new to Aurora and am having trouble simulating the example design the core generated. When I execute sample_tes...
1 comments posted 20yrs
posted by catcall_13
1 comments posted 20yrs posted by catcall_13

xst:What happened here?

Riddle:Where did that +64[ns] on source/dest clk come from?? ==========================================================...
2 comments posted 20yrs
posted by mleikvol
2 comments posted 20yrs posted by mleikvol

ABEL to VHDL translate

Hi all, can someone help me to translate following ABEL code to VHDL on Xilinx. -- BOOT pin istype "reg_d"; -- !IOWR pi...
2 comments posted 20yrs
posted by photodose
2 comments posted 20yrs posted by photodose