Riddle:Where did that +64[ns] on source/dest clk come from??
========================================================================= Timing constraint: TS_CORECLK = PERIOD TIMEGRP "NET_CORECLK" 7.800 nS HIGH
3.900 nS WARNING:Xst:2245 - Timing constraint is not met. Clock period: 66.690ns (frequency: 14.995MHz) Total number of paths / destination ports: 164005 / 21159 Number of failed paths / ports: 75783 (46.21%) / 4474 (21.14%)------------------------------------------------------------------------- Slack: -58.890ns Source: sym/BLKRAM (RAM) Destination: sym/tEMPTY (FF) Data Path Delay: 5.928ns (Levels of Logic = 2) Source Clock: DDR_CKFB1 rising 2.0X +64 at 0.693ns Destination Clock: DDR_CKFB1 rising +64 at 1.387ns
Data Path: sym/BLKRAM (RAM) to sym/tEMPTY (FF) Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ RAMB16_S18_S36:CLKB->DOPB3 2 2.394 0.903 sym/BLKRAM (sym/parbit) LUT4_L:I3->LO 1 0.551 0.126 sym/earlyempty1 (sym/earlyempty) LUT4:I3->O 1 0.551 0.801 sym/_n02221 (sym/_n0222) FDPE:CE 0.602 sym/tEMPTY ---------------------------------------- Total 5.928ns (4.098ns logic, 1.830ns route) (69.1% logic, 30.9% route)