Field-Programmable Gate Arrays

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ABEL to VHDL translate

Hi all, can someone help me to translate following ABEL code to VHDL on Xilinx. -- BOOT pin istype "reg_d"; -- !IOWR pi...
2 comments posted 20yrs
posted by photodose
2 comments posted 20yrs posted by photodose

Newbie to FPGA

Hi, I am a pre-si verification engineer looking to learn HW design, synthesis and P&R through FPGAs. (I am already very...
12 comments posted 20yrs
posted by writeanand
12 comments posted 20yrs posted by writeanand

pad issue

Dear All, As a beginner of IC designer, I was confused with PAD connector, why should we use PAD for top's pin. For inc...
0 comments posted 20yrs
posted by kelvins.huang
0 comments posted 20yrs posted by kelvins.huang

Temperature sensing diode on Vertex 4

I will be using Vertex 4 (LX60) in my project this chip has two pins TDN_0 and TDP_0 which are supposed to be connected...
2 comments posted 20yrs
posted by vassili.savinov
2 comments posted 20yrs posted by vassili.savinov

High speed differential to single ended

Hi, (This was posted in sci.electronics.design, but I'm reposting it here, as this might be a more fitting place). What...
34 comments posted 20yrs
posted by svasanth
34 comments posted 20yrs posted by svasanth

Floppy to FPGA?

I'm currently working with an old imaging device whose only output is a floppy drive which only allows transferring 6 i...
16 comments posted 20yrs
posted by junkaccount616
16 comments posted 20yrs posted by junkaccount616

Doubts on IBUFGDP

Hi all, I am doing a DDR SDRAM design which is obtained using the MIG tool. The target device is V4LX60. But in that i...
1 comments posted 20yrs
posted by vssumesh_asic
1 comments posted 20yrs posted by vssumesh_asic

Hold margin for asynchronous Interface

Hello, I am doing some Excel timing analysis of asynchronous interface. I am finding difficult in formulating the formu...
1 comments posted 20yrs
posted by praveenkumar.bm
1 comments posted 20yrs posted by praveenkumar.bm

bga routing

Hi all, as many of you may know after all my posts, I'm working with a Spartan3 in the FT256 BGA package. Could anyone...
10 comments posted 20yrs
posted by marco
10 comments posted 20yrs posted by marco

library for lmb

hi all.. like there is library for opb, opb_ipif_v3_01_a... what and where is the library for lmb.. also with this if a...
0 comments posted 20yrs
posted by vidyutg
0 comments posted 20yrs posted by vidyutg

How process statement works in vhdl

Hello, I a newer to vhdl. I am trying to change my algorithm form matlab to vhdl. I met RAMs conflict when I did it. **...
2 comments posted 20yrs
posted by threeinchnail
2 comments posted 20yrs posted by threeinchnail

Virtex2-Pro local clocking...

Xilinx has an appnote (XAPP609) describing local clocking for a Virtex2 part. The appnote describes bringing a clock fo...
4 comments posted 20yrs
posted by johnp3+nospam
4 comments posted 20yrs posted by johnp3+nospam