Quartus 6.0 Fitter Critical Warning

I compiled my Design with the new version 6.0 of Quartus and get much more Warnings :-( Especially a Critical Warning of the Fitter disconcerts me:

Critical Warning: Ignored Power-Up Level option on the following nodes -- nodes are set to power up low Critical Warning: I/O cell "i2c_core:inst33|i2c_master_top:inst|i2c_master_byte_ctrl:byte_ctrl|i2c_master_bit_ctrl:bit_ctrl|c_state.idle" will power-up low Critical Warning: I/O cell "i2c_control:inst32|i2c_todo.test_i2c" will power-up low Critical Warning: I/O cell "i2c_control:inst32|i2c_state.write_i2c_core_reg" will power-up low Critical Warning: I/O cell "i2c_core:inst33|i2c_master_top:inst|i2c_master_byte_ctrl:byte_ctrl|\statemachine:c_state.st_idle" will power-up low

This I/O cells are the states of the state machines. How can the state machines be in the right state if the power-up level is not correct initialized ??? The new compilation works anyway!!! Can someone explain it to me???

Thanks, Manfred

Reply to
Manfred Balik
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If you've properly coded your state machine, then they should be put into the proper state by some form of reset signal that occurs, not as a result of some 'power-up' default.

Either your state machine is coded properly but there is an extraneous 'initial' value (see code snip below) or you're just getting lucky....for now. If it's the 'lucky' option, then your luck will run out on you, investigate the code.

Possible source of the problem (assuming VHDL source)

-- In your signal declarations (or variables depending on your coding style) is something like this...

type t_The_States is (Idle, Do_Something, Do_Something_Else, Done); signal Current_State: t_The_States := Idle;

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Reply to
Manfred Balik

It's generally a good idea to understand the source of a 'critical' warning...actually not a bad practice to understand the source of 'not so' critical warnings too. You didn't say whether the place in the code where the signal is actually declared has an initial value assigned to it. Look for the place where the signal is declared and see if it looks anything like...

signal Current_State: t_The_States := Idle;

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Hello Manfred,

We have investigated this and discovered that the message"Critical Warning: Ignored Power-Up Level option on the following nodes --..." is a side effect of a Quartus bug. This bug occurs if there is a State Machine Synthesis with the following conditions:

  1. The State Machine is specified in VHDL.
  2. The State Machine inferred by Quartus Integrated Synthesis (quartus_map) does NOT have a reset signal in it.
  3. State Machine Processing is set to either Auto or One-Hot
  4. Quartus II 6.0 is being used.

If your state machine has a reset in it you can ignore this message. Your design will provide expected results on the board. If your state machine does not have a reset you will need to add a reset to it, else it will not work on the board. This bug exists in Quartus II 6.0 only. It has been fixed in Quartus II 6.0 SP1 which will be released early next week (about June

24th, 2006).

We apologize for any inconvenience this may have caused.

Hope this helps, Subroto Datta Altera Corp.



Reply to
Subroto Datta

Thanks KJ, I have forgotten to say: there is no initial value assigned in the declaration :-((( The code is written correctly (I have checked it, because it's not written by me), and I'm using the same structures you described in my own codes for years ... but this critical warning is new since Quartus 6.0 :-((( and today I have compiled the project several times and it works fine on the FPGA every time!

"KJ" schrieb im Newsbeitrag news:9l9mg.47540$ snipped-for-privacy@newssvr27.news.prodigy.net...

Reply to
Manfred Balik

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