Field-Programmable Gate Arrays

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Achieving timing in Xilinx EDK designs

Hi all, I was wondering if anyone would be willing to share their experiences with regards to what can be done when a d...
8 comments posted 20yrs
posted by mbmsv
8 comments posted 20yrs posted by mbmsv

Optimization of Multiplication in FPGA

hi, there in my project, i need to do some multiplication. and i optimized the multiplicand to numbers like 0.75, 0.625...
2 comments posted 20yrs
posted by agou.win
2 comments posted 20yrs posted by agou.win

is picoblaze worth in my project?

Hi all, I'm doing few tests in these days with the PicoBlaze and it seems to work just fine. Now, in my project, where...
3 comments posted 20yrs
posted by marco
3 comments posted 20yrs posted by marco

stimulus for FPGA

I am planning on buying either a Xilinx Spartan or Altera Development Kit to test out some designs on FPGA. (I am New t...
10 comments posted 20yrs
posted by writeanand
10 comments posted 20yrs posted by writeanand

Xilinx RocketIO receiver reset problem

I'm connecting a V2Pro Rocket IO to a Agilent optical interface and am having problems getting the RocketIO receiver to...
2 comments posted 20yrs
posted by johnp3+nospam
2 comments posted 20yrs posted by johnp3+nospam

Aurora 4 byte interface

Hi to all I am new to group. i am working on aurora protocol. i am stuck as want to use aurora protocol fo r 4 byte int...
1 comments posted 20yrs
posted by bkapil82
1 comments posted 20yrs posted by bkapil82

Spartan 3E Starter Kit - diff b/t rev. C and D?

Can anyone tell me what Xilinx changed between rev C and rev D of the Spartan 3E Starter kit board? By the way, why the...
1 comments posted 20yrs
posted by cole
1 comments posted 20yrs posted by cole

RS232 to access TX registers of Aurora

Hi, I have implemented the Aurora protocol on the V2PRO FF672 FPGA. As part of testing, I need to access the TX data on...
13 comments posted 20yrs
posted by vivek.menon79
13 comments posted 20yrs posted by vivek.menon79

Amirix AP120, U-Boot and uartlite

Hi, since the license of the "original" uart-port is expired, I'm trying to use the uartlite ip core with u-boot and it...
0 comments posted 20yrs
posted by awu.al888
0 comments posted 20yrs posted by awu.al888

Remote access to Altera FPGA via jtagd in Linux

Hi All, I just needed to program and debug my Altera FPGAs remotely. So I've prepared a small script on the remote mach...
2 comments posted 20yrs
posted by wzab
2 comments posted 20yrs posted by wzab

Xilinx Library Conversion

Hi All, My Goal is to use some librarys I have for Xilinx ISE 8.1 with Cadence. The way I thought of going about this i...
0 comments posted 20yrs
posted by DanielJDouglas
0 comments posted 20yrs posted by DanielJDouglas

Linking/mapping code sections with Xilinx EDK

I'm using a V2Pro based eval board with a simple set of frimware and software files. The software set includes the Xvec...
2 comments posted 20yrs
posted by sgfallows
2 comments posted 20yrs posted by sgfallows