Field-Programmable Gate Arrays

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using Celoxica's RC10 with microblaze's EDK kit

Hi, has anybody used before Celoxica's FPGA board RC10 with Xilinx's EDK kit? Somehow, the bit stream I create, yields...
0 comments posted 20yrs
posted by chrisdekoh
0 comments posted 20yrs posted by chrisdekoh

Xilinx XC4VSX25 development board?

Hi, I am looking for an FPGA development board that can host a Xilinx Virtex-4 XC4VSX25 device, because it has 128 mult...
2 comments posted 20yrs
posted by PeterMoreton
2 comments posted 20yrs posted by PeterMoreton

Spartan-3 starter kit strange problem

Dear All, I'm having a strange problem with my design that is driving me nuts... I'm a newcomer to FPGA in general and...
2 comments posted 20yrs
posted by jmariano
2 comments posted 20yrs posted by jmariano

cache aware programming

Hi all, I am using PowerPC on Virtex II Pro. The whole program is bigger than the cache, I suspect though that most of...
5 comments posted 20yrs
posted by eascheiber
5 comments posted 20yrs posted by eascheiber

Actel FUSIN chips are real !

Hi Actel FUSION kit that I had ordered in DEC 2005 (was supposed to be off-the-shelf !) arrived today. Only 6 months de...
1 comments posted 20yrs
posted by Antti.Lukats
1 comments posted 20yrs posted by Antti.Lukats

PCI Express - Root Complex Emulation

Hi there guys, I'm after some help with creating a VHDL testbench model for Root Complex Emulation. My system has an FP...
0 comments posted 20yrs
posted by johnnynorthener
0 comments posted 20yrs posted by johnnynorthener

Stratix column and row pins

An Altera application note (AN-349) recommends placing certain outputs on column pins and others on row pins. My questi...
2 comments posted 20yrs
posted by rreuter
2 comments posted 20yrs posted by rreuter

xst can, but vcomp can't

Error from vcom: Attribute "event" requires a static signal prefix. Xst handles this very nice.. Are there any tricks a...
5 comments posted 20yrs
posted by mleikvol
5 comments posted 20yrs posted by mleikvol

comp.arch.fpga : Selection of Device

Hi all, We want to implement a design in a spartan - 3. and select a device (in terms of system gates) at the initial st...
9 comments posted 20yrs
posted by gavatepravin
9 comments posted 20yrs posted by gavatepravin

Synplicity PREMIER

Hey, I was just wondering if any of you have used/are using/have evaluated Synplicity PREMIER? it seems like an interes...
0 comments posted 20yrs
posted by tim.verstraete
0 comments posted 20yrs posted by tim.verstraete

keys to the Kingdom

Annoyed Crypto Folks, The latest announcement of "security" is just more than a little annoying: http://biz.yahoo.com/p...
35 comments posted 20yrs
posted by austin
35 comments posted 20yrs posted by austin

For Broaddown2 Owners

For all that have asked the first details of the Virtex-4 Swinyard1 module are now posted on the website at http://www....
0 comments posted 20yrs
posted by removethisthenleavejea
0 comments posted 20yrs posted by removethisthenleavejea

Instrumentation Technologies

Hi there, On the look out for an FPGA system, have had a look on the web, came across a company called Instrumentation...
0 comments posted 20yrs
posted by clairm
0 comments posted 20yrs posted by clairm