Latest threads in Field-Programmable Gate Arrays

XST crashes & websupport denies access

Sorry for the uninteresting post, but I was trying my Altera design in ISE 8.1i and XST crashed immediately with FATAL_...

0 20yrs

tommy.thorn

0 20yrs tommy.thorn

Detachable Virtex-II Pro/Virtex-4 FX module with Rocket I/O

Hi, I am searching for a detachable Virtex-II Pro or a Virtex-4 FX series FPGA with rocket I?O capability. I do not wan...

5 20yrs

vivek.menon79

5 20yrs vivek.menon79

SerDES with FPGA Rocket I/O, Aurora at 40 Gbits/sec???

Hi, I am currently using the Virtex-II Pro FPGA FF672 evaluation board from Xilinx. I have implemented the Aurora proto...

8 20yrs

vivek.menon79

8 20yrs vivek.menon79

using Celoxica's RC10 with microblaze's EDK kit

Hi, has anybody used before Celoxica's FPGA board RC10 with Xilinx's EDK kit? Somehow, the bit stream I create, yields...

0 20yrs

chrisdekoh

0 20yrs chrisdekoh

Xilinx XC4VSX25 development board?

Hi, I am looking for an FPGA development board that can host a Xilinx Virtex-4 XC4VSX25 device, because it has 128 mult...

2 20yrs

PeterMoreton

2 20yrs PeterMoreton

Spartan-3 starter kit strange problem

Dear All, I'm having a strange problem with my design that is driving me nuts... I'm a newcomer to FPGA in general and...

2 20yrs

jmariano

2 20yrs jmariano

cache aware programming

Hi all, I am using PowerPC on Virtex II Pro. The whole program is bigger than the cache, I suspect though that most of...

5 20yrs

eascheiber

5 20yrs eascheiber

Actel FUSIN chips are real !

Hi Actel FUSION kit that I had ordered in DEC 2005 (was supposed to be off-the-shelf !) arrived today. Only 6 months de...

1 20yrs

Antti.Lukats

1 20yrs Antti.Lukats

PCI Express - Root Complex Emulation

Hi there guys, I'm after some help with creating a VHDL testbench model for Root Complex Emulation. My system has an FP...

0 20yrs

johnnynorthener

0 20yrs johnnynorthener

Stratix column and row pins

An Altera application note (AN-349) recommends placing certain outputs on column pins and others on row pins. My questi...

2 20yrs

rreuter

2 20yrs rreuter

xst can, but vcomp can't

Error from vcom: Attribute "event" requires a static signal prefix. Xst handles this very nice.. Are there any tricks a...

5 20yrs

mleikvol

5 20yrs mleikvol

comp.arch.fpga : Selection of Device

Hi all, We want to implement a design in a spartan - 3. and select a device (in terms of system gates) at the initial st...

9 20yrs

gavatepravin

9 20yrs gavatepravin

Synplicity PREMIER

Hey, I was just wondering if any of you have used/are using/have evaluated Synplicity PREMIER? it seems like an interes...

0 20yrs

tim.verstraete

0 20yrs tim.verstraete

keys to the Kingdom

Annoyed Crypto Folks, The latest announcement of "security" is just more than a little annoying: http://biz.yahoo.com/p...

35 20yrs

austin

35 20yrs austin

For Broaddown2 Owners

For all that have asked the first details of the Virtex-4 Swinyard1 module are now posted on the website at http://www....

0 20yrs

removethisthenleavejea

0 20yrs removethisthenleavejea

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