Hi, I have implemented the Aurora protocol on the V2PRO FF672 FPGA. As part of testing, I need to access the TX data on the aurora links through RS232 interface as well. Now the problem I have is that the avbl project in XPS has a rx and tx port (std_logic) and the data I need to send is atleast 16 bits. How do I access or interface the register outputs from Aurora to RS232?? Thanks, Vivek
It's fairly easy to make a hack RS-232 transmitter. It's just a shift register preloaded with the data and start/stop bits. For 16 bits of data, I'd use a 20 bit shift register - 2 8-bit bytes with start and stop bits on each.
You can probably sort out all the LSB/MSB first and inversions by reading the specs carefully enough. It's probably simpler to put a scope on the cable to your PC and make it send a known pattern.
You (probably) don't need fancy RS-232 level shifters. Most RS-232 receivers will do the right thing if you feed them a 3V CMOS signal.
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Hi, I am not sure about this and hence the modified question: After designing the Aurora protocol and implementing it, I want to access the data values using my PC. For this purpose, I thought of sending the tx values through the RS232 port of the PowerPC. However, I am having a problem. I am not able to access the RS232 access ports. The files are proprietary of XIlinx EDK and cannot be modified...( iam talking abt "opb_uartlite.vhd" and it's rx and tx versions). I also tried adding the system.xmp file to my ISE project but it's useless as no ports are avbl for sending the tx data to the RS 232 block.
What is the easiest way to do accomplish this task?? I also gather that if this can be figured out, I can in the future access different blocks written in ISE using PPC and output values on RS232. The values inhaled from RS232 can be used for further processing using Matlab, etc.
Thanks, Vivek
Hal Murray wrote:
I am not really sure what you are trying to do. Are you trying to route the output of the transceiver to a RS232 UART? If so, even if you managed to do so, it wouldn't be very useful; there's no way multi-gigabit data rates can be sustained over RS232 (or multi-megabit, for that matter!). Are you trying to send data values to both the MGT and to the RS232 UART? If so, you will have to deal with the difference in speed between the two. However, if you can live with that that, coding a UART in HDL isn't too hard.
- Nathan
actually I just need to transmit the values on RS232 UART core. I am not too bothered about the speed. I just want the values on the PC. most of the RS232 UART cores(atleast the one on the opencores.org site and one referenced by the HERON IP ) do not tell how the data is visible in the terminal program. I have now two VHDL projects of the RS232 but they don't work at least I don't see any data on the terminal window. So I am now considering sending the data to the PPC that will in turn send it to the RS232 UART core.. Lemme know if anyone has had similar problems. Thanks, Vivek
Nathan Bialke wrote:
You likely will need to convert the data to ASCII, if you want it to show up on a terminal. That is quite easy to do.
You send one nibble (4 bits) at a time. If the nibble is between 0-9, then add 0x30 (hex 30). If between a-f, add 0x60. It should be easy to figure out how to do that in VHDL/Verilog. That will give you a hex display.
New problem: When I send the 8-bit test data like for eg.X"31", it should appear on the screen as "01".However this is not taking place. The terminal has baud rate 19200, 8 data bits, 1 stop bit and no flow control. what do I have to specify as start and stop bits?? Moreover I am using the files obtained from Heron Engg...IF anyone has worked on this, lemme know. Thanks, Vivek
Vivek Men> Thanks Duane.
I don't know what Heron Engg is. But X"31" will display as "1" not "01".
Have you simulated it and seen what the output looks like? The output should be high when not sending data, there is a single bit '0' as the start bit, then the 8 bits of data LSB first, then a '1' stop bit. That can be immediately followed by another start bit if more data is ready to be sent, else the output remains at '1' until more data is ready to be sent. Each bit should be 1/19200 seconds or approximately 52uS, but that does not need to be exact; a few percent difference is tolerable.
There should be an RS232 interface chip between the FPGA and your serial cable.
Hi I am using Ken Chapman's UART cores described in xapp223.pdf from Xilinx. I am having mapping errors. Has anyone worked on this?? Thanks, Vivek
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