Field-Programmable Gate Arrays

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"Large" memory array in VHDL

My application needs a somewhat large memory array, for constant (every clock cycle) sequential read/write access -- th...
9 comments posted 20yrs
posted by alexmchale
9 comments posted 20yrs posted by alexmchale

Can I use all 18bits of a BlockRAM?

When I use FPGAs of Xilinx, the BlockRAM is 1K * 18bit, but the data width I can actually use is only 16bit. The other...
14 comments posted 20yrs
posted by lizhongqi
14 comments posted 20yrs posted by lizhongqi

mig_ddr_controller

hi, Does the simulation model provied by the MIG tool work with synthesized simulation model. When i simulated the code...
0 comments posted 20yrs
posted by subin.82
0 comments posted 20yrs posted by subin.82

Weird timing failure

Hello, I am using Xilinx ISE 7.1 and VHDL for a project deployed in a Virtex2 FPGA. I place&route and then I run the st...
2 comments posted 20yrs
posted by kasty.jose
2 comments posted 20yrs posted by kasty.jose

Xilinx ML403 hard mac (xapp443)

Hi, I have been using "Ethernet Cores Hardware Demonstration Platform" with ML403 board and I got very good speed resul...
1 comments posted 20yrs
posted by misiu75
1 comments posted 20yrs posted by misiu75

single pad to pad timing in ISE

I am trying to constrain a single path through my V4 fpga in ISE 6.3. In the VHDL source it simply connects an input pin...
2 comments posted 20yrs
posted by someone
2 comments posted 20yrs posted by someone

ADPLL (50Hz to 2kHz)

Hello all, I would like to learn if there is an open source for an adpll. I need to lock a 2kHz sync signal to 50Hz main...
1 comments posted 20yrs
posted by rasit.sahin
1 comments posted 20yrs posted by rasit.sahin

ASCI to FPGA - require details

Hello experts, Would like to hear from you regarding the precautions, the common practices and problems that arise when...
4 comments posted 20yrs
posted by g.shrinivasan
4 comments posted 20yrs posted by g.shrinivasan

Altium Live Desing Eval and Linux

Is there an implementation of Linux for the Live Design Eval Board(Xilinx). May be a version of uCLinux for Mircoblaze?...
3 comments posted 20yrs
posted by erixx
3 comments posted 20yrs posted by erixx

UCF File : LOC signal syntax

Hello everybody. I use Xilinx (ISE 6.2.03i) and Mentor (Precision RTL 2004) tools. I have an issue when I specify the L...
0 comments posted 20yrs
posted by gguichal
0 comments posted 20yrs posted by gguichal

PPC and Chipscope?

I am starting a new design using V4FX parts. I have only one JTAG connection so far. Is it possible to simultaneously r...
8 comments posted 20yrs
posted by someone
8 comments posted 20yrs posted by someone

Properties of some pins of Vertex4

Hello All, Could anyone please tell me: * Whether I can use "VREF" pins for LVDS output? * What is HSWAPEN exactly for T...
1 comments posted 20yrs
posted by
1 comments posted 20yrs posted by