"Large" memory array in VHDL

If you want to do it all internally, the only part big enough is the XC3S1600E. However, you could simply plop on an external SRAM, have enough RAM left over for growth, and get by with a MUCH smaller FPGA. Even better would be an appropriately sized external dual-port RAM. This would allow you to just implement your control logic and data interface in the FPGA, which (depending on your application) could be a much smaller device.

FPGA's make for some very expensive RAM. If you need RAM in bulk, it's generally better to just add RAM unless you have some other constraint that forbids it.

This is along the lines of what I expected. Dual port ram is definitely a possibility, do you have any suggestions as to a part? Like I said, I'd be looking for a minimum of 64KB. On one side of the DP RAM would be the Spartan-3E, and on the other would be a NetBurner module (a pretty average microcontroller).

Thank you!

Alex McHale

Alex, what sort of clock speed is the uC running at?

One solution is to pipeline the uC access to the ram through the FPGA then alternate access between the uC interface and the FPGA process that's doing the clever bits.

If the uC clock is slow this becomes much easier to implement.

Nial

It depends on the size of your fpga.

Alex escreveu:

I think you'll find that dual port RAM makes the FPGA look cheap. Dual port RAM devices are not generally commodity items, and the ones that are out there tend to dissappear into no longer available land pretty quickly. Since you already have the FPGA in the system, use the FPGA as an interface to a standard single ported RAM and time-multiplex the access. You'll need 2x the RAM bandwidth, so if you are limited in the clock period, double the width of the memory to make up for the slower time-multiplexed access. Use a few of the dual ported BRAMs in the FPGA to buffer data into and out of the SRAM and for clock domain crossings.

Thanks to everyone who has replied.

Can anyone point me to a good resource on learning to interface the FPGA with a RAM chip? I'm using VHDL for everything in the FPGA. The more example VHDL I can see, the better.

This is a project that landed in my lap that I'm having to learn a lot for as I go. The more resources I have to learn how to use this FPGA and VHDL, the better.

Thank you.

Alex McHale

The FPGA and RAM datasheet are very good starting points. The interface, well, the IO pins are there just for that purpouse.

You may try google, opencores, hamburg hdl archive...

Regards,

Alex escreveu:

This may be a good start: