can't read device ID xcv200....what about the PROGRAM pin

blisca schrieb:

Hi I have succesfully soldered wires to Virtex 2000 BGA and the proto did work

prog_b needs to have an pullup to logic high level

xilinx datasheet says it has internal pullup but on Virtex family JTAG config does not work without external pullup, that is the JTAG chain is accessible but configuratio fails.

minimal connections are

GND VCCINT VCCIO in the bank that supply JTAG PROG_B pullup JTAG pins

thats all!

if those connections are ok the FPGA should get configured over JTAG

Antti

for reading the device ID how should the PROGRAM pin be ?

thank you all (i'm still spending hours and days trying to do it,no way....no activity on TDI or TDO)

here ,once ,more the things that i did:

i connected just one 1.8V supply to the VCCINT of the fpga(pin A9),it is not easy to test it (soldering wires on a bga as i do is even worse ...)but it looks that it should be enough for the core,correct???or i need to

i connected in 7 points the 3.3VCCO(A2,B2,B12 , A13,G12,N1,M2) and the ground in 3 points(A1,J1,N12)

i connected the jtag signals,TCK,TDI,TMS,TDO(this one to the level amplifier)

I connected PROGRAM fixed to 3.3V,then i tried to connect it with TMS,same result.....

I left M0 and M2 open,and them are high,M1 tied to ground,this for choosing boundary scan mode

using the debug chain utility i verified that the signals are working but i noticed that there is no movement on TMS,and of course on TDO

there is something else missing?

Thank you to everyone in the group that will help me or just will read this

Diego

blisca schrieb:

uups! I yielled at Xilinx guy about him commenting about VCCAUX, well on Virtex-E it is also not available so it is no problem anyway.

again - M0,M1,M2 - DONT CARE pullup of PROG_B - either 1.8 or 3.3V should be ok

but even with PROG_B pulled down JTAG chain should be scannable can you see the IDCODE when you scan the chain?

Antti

Aurelian Lazarut schrieb:

Well to MY knowledge Virtex-E has also no VCCAUX !?

Antti PS To OP, I probably did not say strong enough: for reading of IDCODE over JTAG the prog_b is "DONT CARE" only issue is (or can be) that actualy configuration may fail without pullup.

Thank you again to all that answered or only spent their time reading this post. Antti wrote

about pull-ups: wich high level?1.8V or 3.3V? (i forgot to say in the subject that i'm working,but i should better say "crying",on a xcv200E )

and what about the MODE?should i use pull-ups or not? this table is still not clear to me......does it means that if i dont use external pull-ups resistors(wich value?) should i use 1 0 1 with M1 connected to ground and M2 and M0 connected directly to.......VINT or VCCO?In few words,what is the correct mode for phisically implement the correct configuration?

Configuration Mode M2 M1 M0 Pull-ups Master Serial 0 0 0 No Slave Serial 1 1 1 No SelectMAP 1 1 0 No Boundary Scan 1 0 1 No xilinx datasheet says it has internal pullup but on Virtex family JTAG

blisca schrieb:

sure you can use the impact "debug mode"

connected your cable TDI-TDO and shoft some pattern and observer results, eg

Antti

can i do it with iMPACT?or only from line comands?thank you

PS sorry again because i forget to type the "E", xcv200E

activity

those

Thank you Bob but no doubt about the wires of my jtag controller,they have different color,using the debug chain of iMPACT i can verify the toggling of the signals until the ball pin on the FPGA itself