Field-Programmable Gate Arrays

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Chaos in FF metastability

I've been reading about chaos theory and it occurred to me that metastability might be a chaotic process. It seems some...
30 comments posted 20yrs
posted by spamgoeshere4
30 comments posted 20yrs posted by spamgoeshere4

design in vsprom

I have a design for vsprom.My idea is that config FPGA with Xilinx CPLD and parallel flash memory.The design is correct...
0 comments posted 20yrs
posted by wuyi316904
0 comments posted 20yrs posted by wuyi316904

LwIP

Hey! Has anyone managed to get LwIP running on a Xilinx Virtex 2 Pro with only on-chip memory? Best regards, Hampus
0 comments posted 20yrs
posted by hampus.thorellNOSPAM
0 comments posted 20yrs posted by hampus.thorellNOSPAM

next EDK service pack release date?

Hi I think Xilinx has said the service packs should come once a months? So is the EDK service pack delaying or may ther...
2 comments posted 20yrs
posted by Antti.Lukats
2 comments posted 20yrs posted by Antti.Lukats

Timing constraints on ISERDES

Using the ISERDES primitive in Virtex 4 in DDR mode (for data input from an ADC), what timing constraints should be app...
0 comments posted 20yrs
posted by tom.derham
0 comments posted 20yrs posted by tom.derham

Synthesis changes after ISE upgrade

I just upgraded ISE 6.3.03 to 8.1 and already I am experiencing varying synthesis results. For one thing I do not infer...
2 comments posted 20yrs
posted by yaseenzaidi
2 comments posted 20yrs posted by yaseenzaidi

how to use the xilinx 18v04 config fpga?

Hi,I need 18v04 to config fpga(for example virtex),when the 18v04 is on PCB board,it can work correctly.When I use jump...
1 comments posted 20yrs
posted by wuyi316904
1 comments posted 20yrs posted by wuyi316904

How to trigger write signal and read sigal

I want to test uart function only. Data is transmitted from matlab to FPGA board(uart), and is sent back to matlab. I h...
0 comments posted 20yrs
posted by threeinchnail
0 comments posted 20yrs posted by threeinchnail

component instantiation ISE7.1

hi, Iam trying to instantiate a component from my user_logic_ip.vhd : signal h:std_logic_vector(0 to 31); signal k:std_...
12 comments posted 20yrs
posted by rgarik
12 comments posted 20yrs posted by rgarik

stable reset in fpga

I want to know how I can reset the logic in fpga and make the least metastable.I use 2 clock in fpga and if it is nesses...
15 comments posted 20yrs
posted by bjzhangwn
15 comments posted 20yrs posted by bjzhangwn

Xilinx System Generator Part List Problem

I'm using ISE WebPack 8.1.03i, System Generator 8.1.01, Matlab R14 SP3 The problem is related with the System Generator...
0 comments posted 20yrs
posted by patrik.camilleri
0 comments posted 20yrs posted by patrik.camilleri

register state when power on

I want to know the registers state after the configurations(altera)
1 comments posted 20yrs
posted by bjzhangwn
1 comments posted 20yrs posted by bjzhangwn

Cyclone-II Configuration via a PCI bus

Hi, I've trawled around this group and on the web a little, but haven't found anything to suit my purposes, so I though...
3 comments posted 20yrs
posted by b1uesparx
3 comments posted 20yrs posted by b1uesparx

How to control the uart

Here is my general idea.I generate a matrix in Matlab. I want to transmit the numbers in matrix into FPGA. And these nu...
4 comments posted 20yrs
posted by threeinchnail
4 comments posted 20yrs posted by threeinchnail