Hello everybody. I use Xilinx (ISE 6.2.03i) and Mentor (Precision RTL 2004) tools. I have an issue when I specify the LOC constraints for bit vectors. I use VHDL, and the Xilinx UCF file format is
NET "Whatever" LOC = "P65";
When I add the file to Precison it doesn't like the "". If I change them to parenthesis...
NET "Whatever(0)" LOC = "P65";
it works OK and uses those constraints. The weird thing is that I get the error when Precision calls the Xilinx tools.
Launcher: Executing edif2ngd "whatever.edf" "whatever.ngo" # INFO:NgdBuild - Release 6.2.03i - edif2ngd G.31a # INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. # Writing the design to "whatever.ngo"... # Reading NGO file # "D:/Path/ps/whatever.ngo" ... # Reading component libraries for design expansion... # # Annotating constraints to design from ile "whatever.ucf" ... # ERROR:NgdBuild:755 - Line 3 in 'whatever.ucf': Could not find net(s) # 'ASignal_OUT' in the design. To suppress this error specify the correct net # name or remove the constraint. The 'Ignore I\O constraints on Invalid Object # Names' property can also be set ( -aul switch for command line users). # .. thisd goes away if I chane the UCF vector indexes to parenthesis.
Could it be that Precision writes the EDIF file with () instead of .
Has anybody seen this? Is there any simple solution (command line switch, setting or something) for this?
I know there's ways around this, but I just thought somebody might know how to use this directly.
Thanks a lot, Guillermo