hi how can i instantiate EDN core (exported from PlanAhead) in top level of a verilog design , while the core doesnot have any associated I/O buffers and gives same error in ISE mapping.
using cores exported from Xilinx plan Ahead with verilg design
Jul 05, 2006
2 Replies
you can create a verilog wrapper, keeping the same ports, and instantiate the wrapper in your top level verilog. This wrapper will be empty and XST will cosider it a black box, but ngdbuild should pick up your edif. make sure you place the edif in the design directory. Aurash
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/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
dear Aurash thank you for your helpful reply. It really solved my problem.
regards MH
Aurelian Lazarut wrote:
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